This report describes the design of different amplifiers that are part of an FM transceiver. This is part of a larger project, which has the objective to design a complete FM transceiver from discrete components only, meaning that IC technology is not considered. The circuits designed are two baseband amplifiers, an intermediate frequency amplifier, a low noise amplifier and an RF power amplifier. The baseband amplifiers are implemented with a Darlington pair in common-collector configuration to achieve a high input resistance, low output resistance, and unity gain transfer. The intermediate frequency amplifier is centered at 9.95 MHz with a -3dB bandwidth of 2 MHz. The maximum gain is 40.5 dB and can be lowered with up to 39.7 dB using a potentiometer, based on the emitter degeneration principle. The low noise amplifier has a maximum noise figure of 1.4 dB over the RF carrier band of 88 to 108 MHz. It has a gain of 33 dB, and reaches its 1 dB compression point for an input of -33 dBm. The total harmonic distortion is less than 0.3%. A class E power amplifier is designed with an efficiency of 72.9%, a transmit power of 3.1 W, and a gain of 31.8 dB. Furthermore, this reports also presents a systematic design approach for amplifiers, which illustrate the core principles on which all the designs are based.

This thesis proposes the design of a new type of read-out circuit for a PIN diode used in Scanning Electron Microscope (SEM) applications. The circuit operates in voltage mode (with high input impedance), which offers significant power-saving advantages over the traditionally used current mode (with low input impedance). The final read-out circuit can detect the incoming charge of ∼1000e− with a temporal resolution of 2.5 ns at a frequency of 400 MHz. Post-layout simulation results indicate a promising reduction in power consumption to 188 µW per pixel. At the core of the read-out circuit is a dynamic comparator. The dynamic comparator is designed to operate with low noise at high frequencies while still having a low power consumption. The final comparator has a delay of 240 ps and 140 µV of input-referred noise while consuming 71 fJ/conversion. The comparator has active offset compensation which reduces the offset from 1σ = 5.87 mV to 1σ = 172 µV in 100 ns. The threshold for the dynamic comparator is created by inserting a small charge of 500e− on the detector, whose polarity is opposite to that of the signal. By creating the threshold as a charge, the ratio between the threshold and the signal is made independent of the detector capacitance. The final pixel is implemented in 40 nm TSMC CMOS technology and occupies an area of 80 µm x 98 µm which includes additional circuits designed to measure and quantify the performance of the pixel. The measurement setup is designed but unfortunately, due to delays in the chip delivery, no measurements could be performed