A design of ultra-low phase noise CMOS oscillator based on series-resonance

Master thesis (2023)

Authors

L. GU Electrical Engineering, Mathematics and Computer Science

Contributors

M. Babaie Electronics - EEMCS (supervisor 1)
F. Sebastiano Quantum Circuit Architectures and Technology - EEMCS (coach)
S.M. Alavi Electronics - EEMCS (coach)
A. Kiavar Electronics - EEMCS (coach)
Faculty
Electrical Engineering, Mathematics and Computer Science
Copyright: © 2023 Lunan GU
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Published Date

03-11-2023

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Abstract

The current trend in the state-of-the-art oscillators achieves low phase noise performance. Such stringent performance is demanded in modern Communication Systems. This thesis proposes the design of a CMOS oscillator achieving the ultra-low phase noise. This design is based on TSMC 40 nm technology, the supply voltage is 1.1 V, and the oscillation frequency is fstart=6.65 GHz and fstop=7.58 GHz, the tuning range is calculated to be 13 % with the Phase Noise@ 1 MHz(normalized to 10 GHz) varies from -128.1 dBc/Hz to -130.4 dBc/Hz and Figure of Merit varies from 188.0 dBc/Hz to 190.0 dBc/Hz, consuming average power of 95 mW and the fcorner is 250 kHz. Since the chip is still in fabrication and the final result only includes the simulation result. Further work involves the measurement and performance validation.