A design of ultra-low phase noise CMOS oscillator based on series-resonance

Master Thesis (2023)

Authors

L. GU (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Supervisors

M. Babaie (TU Delft - Electronics)

Faculty

Electrical Engineering, Mathematics and Computer Science, Electrical Engineering, Mathematics and Computer Science

Oscillator CMOS Phase noise Voltage-controlled oscillator

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https://resolver.tudelft.nl/73c3d4ee-a4a4-4903-8044-3d2dfa9bd81f

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Publication Year

2023

Language

English

Graduation Date

03-11-2023

Awarding Institution

Delft University of Technology

Programme

Electrical Engineering

Faculty

Electrical Engineering, Mathematics and Computer Science, Electrical Engineering, Mathematics and Computer Science

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Abstract

The current trend in the state-of-the-art oscillators achieves low phase noise performance. Such stringent performance is demanded in modern Communication Systems. This thesis proposes the design of a CMOS oscillator achieving the ultra-low phase noise. This design is based on TSMC 40 nm technology, the supply voltage is 1.1 V, and the oscillation frequency is f_start=6.65 GHz and f_stop=7.58 GHz, the tuning range is calculated to be 13 % with the Phase Noise@ 1 MHz(normalized to 10 GHz) varies from -128.1 dBc/Hz to -130.4 dBc/Hz and Figure of Merit varies from 188.0 dBc/Hz to 190.0 dBc/Hz, consuming average power of 95 mW and the f_corner is 250 kHz. Since the chip is still in fabrication and the final result only includes the simulation result. Further work involves the measurement and performance validation.

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