Spin qubits in semiconductor quantum dots hold great promises for quantum information processing thanks to their small footprint, long coherence time, and similarities with classical transistors. However, such a new technology comes with new challenges and requires considering new metrics to develop proof-of-principle devices into a technological platform at scale.

Here, we study Si/SiGe heterostructures developed to host single electron spin qubits. We characterize the heterostructure and material stack using different structural techniques and measure the performances of multiple quantum devices with statistical significance. We use classical and quantum metrics to identify the performance-limiting mechanisms and improve them upon modification of selected parameters of the material stack to enable the next generation of spin qubit devices.

The first experiment is about the electrostatics of undoped Si/SiGe heterostructures. We study the semiconductor/dielectric interface between the epitaxial SiGe spacer and the SiOx and AlOx dielectrics. Against the mainstream approach, we grow heterostructures without an epitaxial Si cap. We find an improved interface from a structural characterization and in the two-dimensional electron transport at low temperatures.

The second experiment concerns the charge noise in few-electron quantum dots. We build on the previous results and focus our attention on the thickness of the Si quantum well. In thin quantum wells without a sacrificial Si cap, we find lower charge noise that we attribute to decreased density of remote impurities and misfit dislocations at the SiGe/Si and Si/SiGe interfaces arising from the local quantum well strain relaxation.

The third experiment finds the balance between disorder and the energy splitting of the nearly degenerate conduction band valleys (valley splitting) by fine-tuning the thickness of the Si quantum well. We challenge the apparent dichotomy between these two parameters and demonstrate heterostructures with simultaneously low disorder and high valley splitting. Besides, we give a quantitative estimation of the amplitude of the strain fluctuations in the quantum well arising from the virtual substrate.

The advancements reported in this thesis confirm the steady progress of the Si/SiGe platform towards realizing a full-scale quantum computer.
We summarize the results in the conclusion chapter, where we also highlight the general trends in the spin qubit community and suggest a few knobs to tweak to further improve the material platform.

The rapidly growing number of qubits in semiconductor quantum computers requires a scalable control interface, including the efficient generation of dc bias voltages for gate electrodes. To avoid unrealistically complex wiring between any room-temperature electronics and the cryogenic qubits, this article presents an integrated cryogenic solution for the bias-voltage generation and distribution for large-scale semiconductor spin-qubit quantum processors. A dedicated cryogenic CMOS (cryo-CMOS) demultiplexer and a cryo-CMOS dc digital-to-analog converter (DAC) have been developed in a 22-nm fin field-effect transistor process to control a codeveloped 2-D array designed with 648 single-hole transistors. Thanks to the dissipation below 120 µ W, the whole system operates at temperatures below 70 mK in a custom-built electrical/mechanical infrastructure embedded in a standard single-pulse-tube dilution refrigerator. The bias voltages generated by the cryo-CMOS DAC are demultiplexed to sample-and-hold structures, allowing to store 96 unique bias voltages over a 3 V range with a voltage drift between 60 µ V / s and 18 mV/s. This work demonstrates a tight integration at mK temperatures of cryo-CMOS bias generation and distribution with a dedicated large-scale quantum device. This showcases how this approach simplifies the wiring to the electronics, thus facilitating the scaling up of quantum processors toward the large number of qubits required for a practical quantum computer.

Disorder in the heterogeneous material stack of semiconductor spin qubit systems introduces noise that compromises quantum information processing, posing a challenge to coherently control large-scale quantum devices. Here we exploit low-disorder epitaxial, strained quantum wells in Ge/SiGe heterostructures grown on Ge wafers to comprehensively probe the noise properties of complex micrometre-scale devices, comprising quantum dots arranged in a two-dimensional array. We demonstrate an average low charge noise across different locations on the wafer, providing a benchmark for quantum confined holes. We then establish spin qubit control and extend our investigation from electrical to magnetic noise through spin echo measurements. Exploiting dynamical decoupling sequences, we quantify the power spectral density components arising from the hyperfine interaction with ⁷³Ge spinful isotopes and identify coherence modulations associated with the interaction with the ²⁹Si nuclear spin bath near the Ge quantum well, underscoring the need for full isotopic purification of the qubit host environment.

Addressing and mitigating decoherence sources plays an essential role in the development of a scalable quantum computing system, which requires low gate errors to be consistently maintained throughout the circuit execution. While nuclear spin-free materials, such as isotopically purified silicon, exhibit intrinsically promising coherence properties for electron spin qubits, the omnipresent charge noise, when converted to magnetic noise under a strong magnetic field gradient, often hinders stable qubit operation within a time frame comparable to the data acquisition time. Here, we demonstrate both open- and closed-loop suppression techniques for the transduced noise in silicon spin qubits, resulting in a more than two-fold (ten-fold) improvement of the inhomogeneous coherence time (Rabi oscillation quality) that leads to a single-qubit gate fidelity of over 99.6% even in the presence of a strong decoherence field gradient. Utilizing gate set tomography, we show that adaptive qubit control also reduces the non-Markovian noise in the system, which validates the stability of the gate fidelity. The technique can be used to learn multiple Hamiltonian parameters and is useful for the intermittent calibration of the circuit parameters with affordable experimental overhead, providing a useful subroutine during the repeated execution of general quantum circuits.

Electron-spin qubits in Si/SiGe quantum wells are limited by the small and variable energy separation of the conduction-band valleys. While sharp quantum-well interfaces are pursued to increase the valley-splitting energy deterministically, here we explore an alternative approach to enhancing the valley splitting on average. We grow increasingly thinner quantum wells with broad interfaces to controllably increase the electron wave function overlap with Ge atoms. Quantum Hall measurements of two-dimensional electron gases reveal a linear correlation between valley splitting and disorder-induced single-particle energy-level broadening, driven by increasing alloy scattering at the Si/SiGe interface. We demonstrate enhanced valley splitting while maintaining respectable electron mobility, indicating a low-disorder electrostatic potential environment. Simulations using experimental Ge concentration profiles predict an average valley splitting in quantum dots that matches the enhancement observed in two-dimensional systems. Our results motivate the experimental realization of quantum-dot spin qubits in these heterostructures.

The electrical characterisation of classical and quantum devices is a critical step in the development cycle of heterogeneous material stacks for semiconductor spin qubits. In the case of silicon, properties such as disorder and energy separation of conduction band valleys are commonly investigated individually upon modifications in selected parameters of the material stack. However, this reductionist approach fails to consider the interdependence between different structural and electronic properties at the danger of optimising one metric at the expense of the others. Here, we achieve a significant improvement in both disorder and valley splitting by taking a co-design approach to the material stack. We demonstrate isotopically purified, strained quantum wells with high mobility of 3.14(8) × 10⁵ cm² V⁻¹ s⁻¹ and low percolation density of 6.9(1) × 10¹⁰ cm⁻². These low disorder quantum wells support quantum dots with low charge noise of 0.9(3) μeV Hz^−1/2 and large mean valley splitting energy of 0.24(7) meV, measured in qubit devices. By striking the delicate balance between disorder, charge noise, and valley splitting, these findings provide a benchmark for silicon as a host semiconductor for quantum dot qubits. We foresee the application of these heterostructures in larger, high-performance quantum processors.

We investigate the disorder properties of two-dimensional hole gases in Ge/SiGe heterostructures grown on Ge wafers, using thick SiGe barriers to mitigate the influence of the semiconductor-dielectric interface. Across several heterostructure field effect transistors, we measure an average maximum mobility of ( 4.4 ± 0.2 ) × 10 6 cm 2 / Vs at a saturation density of ( 1.72 ± 0.03 ) × 10 11 cm − 2 , corresponding to a long mean free path of ( 30 ± 1 ) μ m . The highest measured mobility is 4.68 × 10 6 cm 2 / Vs . We identify uniform background impurities and interface roughness as the dominant scattering mechanisms limiting mobility in a representative device, and we evaluate a percolation-induced critical density of ( 4.5 ± 0.1 ) × 10 9 cm − 2 . This low-disorder heterostructure, according to simulations, may support the electrostatic confinement of holes in gate-defined quantum dots.

We grow strained Ge/SiGe heterostructures by reduced-pressure chemical vapor deposition on 100 mm Ge wafers. The use of Ge wafers as substrates for epitaxy enables high-quality Ge-rich SiGe strain-relaxed buffers with a threading dislocation density of ( 6 ± 1 ) × 10 5 cm − 2 , nearly an order of magnitude improvement compared to control strain-relaxed buffers on Si wafers. The associated reduction in short-range scattering allows for a drastic improvement of the disorder properties of the two-dimensional hole gas, measured in several Ge/SiGe heterostructure field-effect transistors. We measure an average low percolation density of ( 1.22 ± 0.03 ) × 10 10 cm − 2 and an average maximum mobility of ( 3.4 ± 0.1 ) × 10 6 cm 2 / Vs and quantum mobility of ( 8.4 ± 0.5 ) × 10 4 cm 2 / Vs when the hole density in the quantum well is saturated to ( 1.65 ± 0.02 ) × 10 11 cm − 2 . We anticipate immediate application of these heterostructures for next-generation, higher-performance Ge spin-qubits, and their integration into larger quantum processors.

As spin-based quantum processors grow in size and complexity, maintaining high fidelities and minimizing crosstalk will be essential for the successful implementation of quantum algorithms and error-correction protocols. In particular, recent experiments have highlighted pernicious transient qubit frequency shifts associated with microwave qubit driving. Work-Arounds for small devices, including prepulsing with an off-resonant microwave burst to bring a device to a steady state, wait times prior to measurement, and qubit-specific calibrations all bode ill for device scalability. Here, we make substantial progress in understanding and overcoming this effect. We report a surprising nonmonotonic relation between mixing chamber temperature and spin Larmor frequency which is consistent with observed frequency shifts induced by microwave and baseband control signals. We find that purposefully operating the device at 200 mK greatly suppresses the adverse heating effect while not compromising qubit coherence or single-qubit fidelity benchmarks. Furthermore, systematic non-Markovian crosstalk is greatly reduced. Our results provide a straightforward means of improving the quality of multispin control while simplifying calibration procedures for future spin-based quantum processors.

Charge noise in the host semiconductor degrades the performance of spin-qubits and poses an obstacle to control large quantum processors. However, it is challenging to engineer the heterogeneous material stack of gate-defined quantum dots to improve charge noise systematically. Here, we address the semiconductor-dielectric interface and the buried quantum well of a ²⁸Si/SiGe heterostructure and show the connection between charge noise, measured locally in quantum dots, and global disorder in the host semiconductor, measured with macroscopic Hall bars. In 5 nm thick ²⁸Si quantum wells, we find that improvements in the scattering properties and uniformity of the two-dimensional electron gas over a 100 mm wafer correspond to a significant reduction in charge noise, with a minimum value of 0.29 ± 0.02 μeV/Hz^½ at 1 Hz averaged over several quantum dots. We extrapolate the measured charge noise to simulated dephasing times to CZ-gate fidelities that improve nearly one order of magnitude. These results point to a clean and quiet crystalline environment for integrating long-lived and high-fidelity spin qubits into a larger system.

We grow 28Si/SiGe heterostructures by reduced-pressure chemical vapor deposition and terminate the stack without an epitaxial Si cap but with an amorphous Si-rich layer obtained by exposing the SiGe barrier to dichlorosilane at 500 °C. As a result, 28Si/SiGe heterostructure field-effect transistors feature a sharp semiconductor/dielectric interface and support a two-dimensional electron gas with enhanced and more uniform transport properties across a 100 mm wafer. At T = 1.7 K, we measure a high mean mobility of (1.8 ± 0.5) × 10 5 cm2/V s and a low mean percolation density of (9 ± 1) × 10 10 cm-2. From the analysis of Shubnikov-de Haas oscillations at T = 190 mK, we obtain a long mean single particle relaxation time of (8.1 ± 0.5) ps, corresponding to a mean quantum mobility and quantum level broadening of (7.5 ± 0.6) × 10 4 cm2/V s and (40 ± 3) μ eV, respectively, and a small mean Dingle ratio of (2.3 ± 0.2), indicating reduced scattering from long range impurities and a low-disorder environment for hosting high-performance spin-qubits.