Spin qubits in semiconductor quantum dots are a compelling platform for large-scale quantum computation thanks to their small footprint, long coherence times, and compatibility with advanced semiconductor manufacturing. Despite the many milestones achieved by the community, a dominant material platform still needs to emerge. Uniquely, in Si/SiGe and Ge/SiGe heterostructures, strain fluctuations in the virtual substrate below the quantum well give rise to non-uniformities that emerge as a periodic roughness at the surface, called a “crosshatch” pattern. With the size of multi-qubit devices crossing the crosshatch wavelength of ∼1µm, a more precise understanding of the effects of these strain fluctuations is necessary. In this thesis, we propose a crossbar grid architecture as a testbed to investigate the disorder at length scales comparable to the cross-hatch and beyond. We design, fabricate, and characterize the first grid of single-hole transistors (SHTs) in Ge/SiGe heterostructures. The grid integrates the shared control of 648 SHTs, of which we successfully operate 647, highlighting the robustness of our design and fabrication flow. We characterize the device uniformity in transport using turn-on thresholds and maximum currents, and the dimensional uniformity with SEM images. We encounter device drift as the most significant obstacle during our measurements, which we explain by the filling of charge traps in or near the dielectric/semiconductor interface. We propose two schemes to help mitigate device drift, which exploit the kinetics of trap filling in both cases. Moreover, we propose a new way to gauge the energy density and kinetics of charge traps via an effective voltage mapping technique. This work demonstrates the feasibility of using a crossbar architecture to achieve a statistical characterization of the material and single-device performance and highlights the importance of improving device stability in Ge/SiGe to aid the future development of reliable quantum devices.
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One of the main components used in superconducting quantum chips is the Josephson junction. Currently when fabricating Josephson junctions, the resistance uniformity at wafer-scale is not optimal. It is also known that an annealing process can alter the junction resistance and with it the qubit frequency. However, laser annealing has only shown to be able to increase the junction resistance. An equally effective and minimally invasive technique to decrease junction resistance is necessary to have full control on frequency
targeting. Thermal annealing in a reducing environment is known to result in a global decrease in junction resistance. To get better control on frequency targeting the techniques could be combined. A die containing not-capped Manhattan type Josephson junctions has been annealed using forming gas at 200°C for 2 minutes, based on a non-linear least squares reciprocal function fit to the data an asymptotic lower bound of 467 μSμm^-2 for the change in conductance per unit area has been found. Smaller junctions with an area
of approximately 0.03 μm² undergo a bigger change in conductance per unit area of around 800 μSμm^-2. Annealing at higher temperatures such as 300 and 400°C results in a decrease of the conductance. There is no substantial change in yield of usable SQUIDs when using a rapid thermal annealing process.
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