Electronic noses (e-noses) play a vital role in the Internet of Things (IoT), functioning as standalone nodes that collect environmental data such as humidity, temperature, and volatile organic compounds (VOCs). This thesis presents the design of a readout circuit for an existing CMOS capacitive sensor array, utilizing a second-order hybrid (active–passive) sigma-delta ADC.
Unlike conventional sigma-delta converters that process voltage inputs, the proposed ADC directly handles capacitance variations. Environmental changes induce shifts in the sensor array’s capacitance, which are converted into current signals using a switched-capacitor technique. The first integrator is implemented passively, comprising an integration capacitor and the equivalent resistance of the switched-capacitor network. The second integrator adopts an active 𝑔𝑚–C structure to enhance node swing and loop gain.
To suppress 1/f noise originating from the transconductance stage, an auto-zeroing technique is employed. The offset is sampled and stored on two dedicated auto-zero capacitors, effectively canceling its influence. As a result, the contribution of 1/f noise to the final output becomes negligible. The primary objective of this work is to ensure that the system’s performance is fundamentally limited by the input thermal noise, with minimal degradation from the 𝑔𝑚 stage and comparator. Fabricated in NXP’s 140 nm CMOS process, the ADC operates at 100 MHz, achieving an SNR of 82 dB and a bandwidth of 12.2 kHz, while consuming only 46 μW of power. The resulting figure of merit (FoM) is 160 dB.

This thesis presents the design of a low-power wireless sensor node intended for deployment in space environments, such as on the lunar surface. The goal was to create a system that is capable of sensing, storing, retrieving, and transmitting data within a very strict power constraints. The node architecture consists of six distinct submodules: a sensor, a processor, a memory unit, a radio, and power management unit. Each submodule has been evaluated for power consumption and functionality. A comprehensive power budget was developed based on real component data.
The study demonstrates that with careful power allocation and system scheduling, essential functionality can be maintained even with limited energy availability. The essential functionalities were subsequently developed and integrated into the individual design blocks. Although some features were deferred due to time constraints, the final design meets the program requirements and provides a solid foundation for future hardware implementation and testing.

This bachelor thesis presents the work of the sub-group ”Mesh Networking” of the larger project ”An Open-Source Platform to Develop Wireless Nodes for Lunar Exploration”. The aim of this project is to design and develop an open-source software to simulate, deploy, and visualize a mesh network to measure radiation on the Shackleton crater. The Shackleton crater is located on the South pole and has a high interest for lunar missions. Given the Moon’s rough terrain and obstacles, a measurement using a rover will be inefficient. By using a wireless mesh network, a robust, scalable network can be created to measure radiation across a wide area. The developed software allows the user to deploy a mesh network with customizable inputs, such as connection radius, number of nodes deployed, and location. It simulates the number of hops from each node to the sink node, the lifetime, and network dynamics. On top of that, the user can input a script with a failure simulation. Additionally, the inter-connection protocols based on IPv6, 6LoWPAN, and RPL were studied and integrated.

This thesis presents the development of an open-source electronic design automation (EDA) toolchain for mixed-signal integrated circuit (IC) design using the Skywater 130nm PDK. The toolchain integrates digital, analog, and mixed-signal flows using OpenLane, Xschem, Ngspice, and ALIGN, among others. It automates key steps such as schematic simulation, layout generation, and verification while remaining accessible and modular. A major contribution is the demonstration of cryogenic simulation support using extracted parameters from transistor measurements at 4K, showcasing the potential for space and quantum applications. The work also includes Docker-based deployment to ensure reproducibility and ease of use across platforms.

Quantum computers are potential next generation computing system, and are expected to consist of millions of quantum bits (Qubits) which are typically required to operate at cryogenic temperature. Electronic devices are used to control and read out qubits, however there are limitations of wiring massive number of electronics and qubits between room temperature and cryogenic environment, which causes a bottleneck for the size-up of the quantum computer. Cryogenic temperature CMOS electronics, which are able to operate at low temperatures and be placed close to qubits have been proposed to overcome this bottleneck.
This work explores superconducting qubit, a type of widely used qubit in latest quantum computers, and the current output DAC designed for flux bias, which is a control method of superconducting qubits. The state-of-the-art DAC designs still face the problem of too high power consumption that restricts placing the control electronics close to the qubits. This thesis proposes a cryogenic current output high compliance regulated Digital-to-Analog converter, reducing the power consumption by 80% comparing to the latest studies.
This thesis proposes an architecture combining a slow DAC array and a fast switch array to realize fast speed while avoiding the high power requirement of high-speed fine DACs. The design uses an operational amplifier to build a feedback loop to regulate a cascoded current mirror array as the core of the high compliance regulated current DAC. The DAC achieves an output range of 0 to 500 𝜇A, with 8.41 nA of accuracy; a sampling rate of 250 MHz and 2.1 ns of rising and falling time. The maximum total power consumption is 179.4 𝜇W, which is less than 20% of the state-of-the-art design examples. The estimated chip area of this design is 2.7 𝑚𝑚2.

Superconducting Nanowire Single-Photon Detectors (SNSPDs) are characterized by high detection efficiency, high counting rates, low dark count rates, and minimal timing jitter, making them indispensable in fields such as quantum information science, free-space optical communication, and fundamental physics. Conventional SNSPD architectures, however, require the superconducting nanowires to be biased with a constant current and necessitate continuously operating readout circuits to capture the output signals. This leads to efficiency issues under prolonged low-load conditions and poses significant challenges for the development of multi-pixel SNSPD arrays. This thesis begins by examining conventional SNSPD designs, critically analyzing the shortcomings of previous active quenching methods, and proposing improvements to the digital sub-circuit. The introduction of a differential amplifier in place of the original single-ended main amplifier successfully addresses output offset issues, pushing the count rate beyond 50MHz. Moreover, this work introduces a novel persistent current SNSPD that leverages the memory characteristic of persistent currents in a superconducting loop, enabling photon detection without the continuous drive from interface circuits, and allowing for unified readout. A design methodology for SNSPD loops is proposed based on various simulation techniques and the physical and electrical characteristics of SNSPDs. This methodology was applied to design multiple samples tailored to different loop coupling scenarios. Additionally, the thesis outlines the biasing and readout logic for the persistent current SNSPD, ensuring independent photon detection without external circuit interference. In the demonstration system, the energy consumption per detection event was measured at 7pJ, with the average power consumption dependent on the frequency of rebias operations.

Shuttling-based single qubit gate is an emerging method for qubit manipulation that offers
significant advantages, including the elimination of RF signals, simplicity, and reduced
charge noise. Despite its potential, the development of specific shuttling pulses for quantum
operations and the design of cryogenic circuits to facilitate these pulses are areas that
remain largely unexplored. This gap has led to the focus of my thesis project: designing an
application-specific circuit to implement shuttling gates.
The contributions of this thesis are twofold. The first part begins with an analysis of
the system Hamiltonian, progressing to the development of pulse compilation methods
designed to implement arbitrary quantum gates across a wide range of sample parameter
variations. This section includes extensive quantum dynamics simulations to determine
the necessary specifications for the supporting circuit.
The second part of the thesis details the design of a cryogenic circuit based on imple-
menting a high-precision, wide-range digital-to-time converter using Intel 16nm FinFET
technology. This segment covers the proposed architecture, sub-circuit schematics, and
performance simulations. The subcircuit achieves sub-picosecond resolution and can ex-
tend to a microsecond-level operational range. It also maintains low power consumption,
with common delay circuits consuming only 2.8𝑚𝑊 and dedicated delay circuits 44𝜇𝑊
for each qubit. This efficiency demonstrates the circuit’s potential to control thousands of
shuttling qubits effectively

This thesis focuses on the design and optimization of Successive-approximation (SAR) Analog-to-Digital Converter (ADC), with a primary focus on enhancing the Bit Error Rate (BER). SAR ADCs are widely used in various applications due to their power-efficient characteristics. The critical point addressed in this research is improving the BER of synchronous SAR ADCs without the necessity to reduce the sampling speed...

To support the exploration of the Moon, wireless sensor networks could be deployed. However, using a very large number of tiny sensing nodes to collect data in such a harsh environment has many challenges. Integrated circuits are exposed to a wide temperature range (-253 °C / +120 °C) during the lunar days and nights. To meet the very constrained power budget of an autonomous node, the node time references must consume ultra-low power while maintaining an accurate frequency. To allow accurate operation over the wide target temperature range and be robust to radiations, this thesis proposes to lock the frequency of a frequency locked loop (FLL) to an LC filter. In the FLL, a high-frequency low-power ring oscillator is locked to a separate LC filter to potentially save power with respect of a standard LC oscillator. To further save power, the FLL is heavily duty-cycled and turned on only to calibrate a lower-frequency oscillator to compensate its drift due to noise and environmental changes, thus achieving ultra-low-power dissipation. This thesis explores the design and implementation of the first LC-based FLL by proposing a system architecture, analyzing its limitations and proposing a transistor-level implementation. The resulting time reference, when implemented in TSMC 40-nm process, consumes 773.29𝜇𝑊 power and achieved an estimated 41.89𝑝𝑝𝑚/ 𝑜𝐶 temperature coefficient within an 0.389𝑚𝑚2 chip area.

This thesis describes the design, implementation, and characterization of integrated RC frequency references. The primary focus of the work is a frequency-locked loop (FLL) architecture, realized in standard CMOS, that digitizes the phase shift of an integrated RC filter, processes the results in the digital domain, and uses it to control an output frequency to maintain its accuracy over temperature variations.....

Quantum computers promise large speedups compared to classical computers for specific classes of problems by exploiting quantum phenomena for computation. Despite notable progress towards larger systems, today's quantum computers still lack the necessary size for realizing many of the anticipated benefits. Scaling to these larger numbers is complicated by the fragility of the qubits, which raises the necessity of operating the quantum computing core at deep cryogenic temperatures to limit the influence of noise. However, in the present experimental setups for quantum computing the electronic interfaces are often based on equipment operated at room temperature. This arrangement creates a potential wiring bottleneck towards cryogenic temperature, that is connected to reliability limitations. A proposed solution to this challenge is moving the interfacing electronics close to the qubits into the cryogenic environment. However, implementation of the electronics at cryogenic temperature places a set of system constraints that prevents directly porting the room-temperature electronics. The most prominent of these constraints is the limited cooling power at deep cryogenic temperature, requiring the interfacing electronics to save power wherever possible. To implement the necessary functions of the interface in practice, CMOS technology is uniquely positioned due to its large scale integration capabilities, low-power digital logic and sustained performance at cryogenic temperature.

In this work, contributions to the readout electronics of quantum computers are made, with an emphasis on the readout of semiconductor spin quantum computers. Readout poses a significant challenge for current spin-qubit systems, especially its scalable integration into the electronic interface. This dissertation can be separated into contributions to the readout of quantum computers in three main categories: cryogenic digitization, cryogenic noise characterization and readout benchmarking.

The wide-band signals present in the frequency-multiplexed RF readout interface require corresponding wide-band digitization capabilities of the associated data converters. In this work, we present robust, power-efficient and high-speed time-interleaved SAR ADC designs adopted to operation at cryogenic temperature to serve this application. These include the first high-speed cryo-CMOS SAR ADC suitable for operation in the RF readout interface, further efficiency improvements to this ADC and finally an ADC tightly integrated with an efficient body-bias enabled dynamic pre-amplifier. The body-bias enabled pre-amplifier also demonstrated excellent room-temperature performance, with the best reported combined power efficiency of a high-speed SAR and driver circuit.
All designs have been realized in a 40nm CMOS technology and characterized at cryogenic temperature.

For the directed design of many of the functions in the electronic interface, accurate models for simulation are required. While significant work has been presented on DC characterization at cryogenic temperatures, comparatively little work covering low-frequency noise is available. To help further development, an extensive low-frequency noise characterization is performed on a 40nm CMOS technology at cryogenic temperature. The results of this characterization allow a broad overview over the low frequency noise behavior of the technology. Given the radical change in temperature between room-temperature and cryogenic temperature, a surprisingly small overall change in the input-referred noise is observed. The most prominent difference is the finding of a systematic Lorentzian feature at cryogenic temperature that is for the first time described here.

Lastly, while promising designs have been suggested for the DC-readout of spin qubits, guidelines for directing such designs have been lacking. In order to provide a set of such guidelines, we first demonstrate that the limits of DC-readout lie significantly beyond current state-of-the-art, with much room for improvement on the electronics. Then, we analyze the voltage amplifier, the transimpedance amplifier, the charge sampling, and the current pre-amplifier by deriving their design equations and trade-offs.
Finally the various architectures are compared with the fundamental limit and suggestions for specific use-cases are give. The results suggest that DC-readout is a promising path for the development of a scalable spin-qubit readout.

Quantum computers, mainly rely on quantum bits (qubits), which need to be operated at cryogenic temperatures. With the need for systems with thousands or even millions of qubits, the challenges of wiring and scalability become more apparent. To address this, several studies focused on the idea of fully integrated cryogenic controller systems. It operates in close proximity to qubits in a deep cryogenic environment. In order to ensure operation over a specific temperature range, accurate temperature monitoring by temperature sensors (TS) is critical in this type of setup. Such sensors should operate efficiently at low temperatures and should operate over an extremely wide temperature range (from 4K to 300K) with high accuracy and energy efficiency. Current TS still faces performance challenges in such applications, especially in temperatures below 200K. CMOS-based smart temperature sensors have the advantages including low cost, compact size, and ease of use. Among the various CMOS sensing elements, Capacitively Biased Diodes (CB-Ds) were chosen for this project. Therefore, in this project, a CB-D-based temperature sensor with a novel hybrid voltage-time domain readout in Intel 16nm FinFET technology is proposed with the capability of operating within a range from 4.2K to 300K.

Based on this topology, a further over-ranging technique is employed, thereby energy efficiency and accuracy are improved. From simulated data, with the supply VDD = 0.90V, an accuracy of +0.5/ − 0.3K with a conversion time of 44.1 µs is achieved. Furthermore, it consumes 21.9 µW, which has a competitive performance with room temperature prior art smart temperature sensors. Based on measurements, a customized smart temperature sensor can be designed. This will allow cryo-CMOS thermal monitoring system to be designed, which will provide an important milestone in the realization of scalable quantum computing.

The concept of quantum computing is gaining increasing popularity in the last years due to its potential for running certain classes of algorithms much more efficiently than classical computation. These algorithms span from simulation of quantum mechanical effects to factorization of large number, from simulation of molecules for drug discovery to encryption of data.
One of the challenges of the current state-of-the-art of quantum computing is related to the scalability of this technology since, in order to solve the aforementioned problems, the required number of logical qubits in a quantum processor is in the order of millions. Qubits are very fragile systems and, to maintain their encoded information intact over time, it is necessary to keep them (most of the existent qubit classes) at very low temperature in dedicated dilution fridges; spin qubits in particular (the type of qubits that this work will focus on) need to be kept at around 2-300mK in most of the technologies available nowadays. Since having millions of big wires coming out of a fridge to control the qubits is nor feasible nor reasonable, it has been
proposed that a big part of the interface electronics is moved from room temperature to cryogenic temperature, close to the qubits.
The readout of a qubit consists in translating its state into a piece of information that can be used for computation in quantum algorithms. In the specific case of spin qubits, the information is encoded in the spin of electrons or quantum states of multiple electrons, when those are subjected to a magnetic field. The weak magnitude of the signal encoding this type of information, together with the temperature at which the system operates result in very strict requirements for power and noise of the integrated circuit.
This work presents a review of the readout process together with the design and simulation of a low frequency readout circuit. Many readout techniques are addressed and pros and cons of each one are discussed before diving into the actual circuit design. The SiGe BiCMOS technology from IHP is analyzed due to its potential for realizing low noise readout circuit. This technology is used in Cadence for simulating and assessing the performance of some proposed readout circuit architectures, namely the Current amplifier, the Voltage amplifier, the Transimpedance amplifier and the Charge amplifier. Eventually, the Voltage amplifier, which shows the more promising results in preliminary simulations, is designed at transistor level and combined with other blocks to realize the whole front-end readout circuit. From the simulation results, it is believed that the circuit can meet the target specification of 10dB SNR and achieve a functional reading at cryogenic temperature with a power consumption lower than 10µW at a speed of 1Ms/s.

As the number of qubits increases, controlling qubits at cryogenic temperatures with electronics at room temperature becomes infeasible due to the vast number of cabling. This necessitates controlling quantum operations on the qubits with a cryogenic interface, which is low power, scalable and maintains qubit fidelity.

In pursuit of this interface, this thesis investigates the two-qubit DAC specifications of both the adiabatic and nonadiabatic CPHASE gate. The DAC specifications are identified using simulation models of spin qubits. The adiabatic signal requirements are found to be lower than the nonadiabatic signals in both sampling frequency and quantization resolution. A new method using spectral analysis on the unitary of the adiabatic operation is used to infer the minimum sampling frequency by applying the Nyquist Criterion and shows why they lose their fidelity as gate time decreases.

A novel two-stage current-switching DAC architecture is proposed, which maintains fidelity operating at 140MHz sampling rate with less than 75 uW of power consumption. The first 6-bit stage maintains CPHASE fidelity for different qubit pairs, while the second 5-bit stage creates the adiabatic pulse. Finally, the DAC is implemented in the Intel 16-nm finFET process.

Single-photon detection is a critical step in both quantum computing and quantum information technology. For instance, the measurement of qubit states and the establishment of entanglement in nitrogen vacancy (NV) center quantum computing requires the detection of single photons. Superconducting nanowire single-photon detectors (SNSPDs) are very competitive devices due to their performance in high detection efficiency, high count rates, low dark count rates, and low jitter. However, the readout electronics are usually implemented at room temperature by connecting the dilution refrigerator through coaxial cables, while SNSPD need to work in a cryogenic environment that is close to the qubits. In order to have better integration and reduce the complexity of the wiring when the number of qubits increases, it is essential to position the electronics close to, or even integrated with, the SNSPD and qubits.
In this thesis, a cryogenic CMOS readout for SNSPD is designed and taped-out using TSMC 40 nm technology. The SNSPD is designed for color-center quantum computing, which is anticipated to work in the wavelength range of 619-620 nm and 625-750 nm, and at a temperature of 1.8 K. The readout electronics are expected to operate at 4 K. The system is required to have a detection efficiency of more than 90 % and a dark count rate of less than 1 Hz. With the help of SPICE dynamic model, the SNSPD is reproduced in Cadence Spectre for circuit design. Active quenching is implemented in the readout architecture, allowing for an increased readout resistor, which improves the output slew rate and count rates without any latching while still keeping a high bias current for a higher detection efficiency. Under a -40 degree Celsius simulation, the readout system achieved count rates greater than 20 MHz, an average jitter of 25 ps rms, and a power consumption of 36 uW, while simultaneously expecting to significantly suppress the dark count rates and after pulses.

To fulfill the vision of scalable quantum computers, cryogenic CMOS is a promising technology to implement the electronic interface for large-scale quantum processors. Research over the years has shown performance improvements in CMOS transistors in commercially viable technology at cryogenic temperatures. While the physics behind the operation of CMOS transistors in cryogenic temperature is known to a great extent, a full-scale compact model is yet not widely available for deep cryogenic temperatures at which qubits operate. For the design of circuits that can be placed in close proximity to qubits, a compatible model needs to be built. In recent years some effort has been made in this direction but most of these are related to DC behavior of the transistor. Very limited work is available that model the RF behavior of transistors at cryogenic temperature across a wide range of bias conditions. As an alternative to a complex physics-based compact model, in this work, we have explored the use of artificial neural networks to model the behavior of CMOS transistors in advanced technology nodes. While a non-linear charge-based model using Adjoint-ANN for deep cryogenic temperature has already been shown as an effective approach, we extend the idea of using ANN to facilitate a model of the CMOS transistors. Transistors from 22nm FDSOI technology were characterized for their S-parameter response at room temperature and 4K for this work.

Input qubit control signals from an arbitrary waveform generator (AWG) operating at room temperature undergo linear dynamical distortions as it traverses various electrical components on the control line connecting to the quantum device.
If uncompensated for, such distortions can have detrimental effects on gate performance, affecting fidelity and even repeatability. Distortions introduced by components at room temperature (e.g., AWG bandwidth, high-pass filtering of a bias tee, and skin effect in instrumentation cable) are easily characterized using a fast oscilloscope. However, distortions introduced by components inside the refrigerator (e.g., low-pass filters, impedance mismatch, skin effect in semi-rigid coaxial cable, and chip packaging) are generally temperature-dependent and are thus best characterized in the cold. Additionally, the on-chip response varies across devices and even between different qubits on the very same device. Evidently, the ideal strategy for characterizing pulse distortion is to use the controlled qubit itself.
The aim of the thesis project is to implement the various, available protocols for the characterization of control pulse distortions on a superconducting quantum hardware and evaluate their individual performances.

The current trend in the state-of-the-art oscillators achieves low phase noise performance. Such stringent performance is demanded in modern Communication Systems. This thesis proposes the design of a CMOS oscillator achieving the ultra-low phase noise. This design is based on TSMC 40 nm technology, the supply voltage is 1.1 V, and the oscillation frequency is f_start=6.65 GHz and f_stop=7.58 GHz, the tuning range is calculated to be 13 % with the Phase Noise@ 1 MHz(normalized to 10 GHz) varies from -128.1 dBc/Hz to -130.4 dBc/Hz and Figure of Merit varies from 188.0 dBc/Hz to 190.0 dBc/Hz, consuming average power of 95 mW and the f_corner is 250 kHz. Since the chip is still in fabrication and the final result only includes the simulation result. Further work involves the measurement and performance validation.