The concept of quantum computing is gaining increasing popularity in the last years due to its potential for running certain classes of algorithms much more efficiently than classical computation. These algorithms span from simulation of quantum mechanical effects to factorization of large number, from simulation of molecules for drug discovery to encryption of data.
One of the challenges of the current state-of-the-art of quantum computing is related to the scalability of this technology since, in order to solve the aforementioned problems, the required number of logical qubits in a quantum processor is in the order of millions. Qubits are very fragile systems and, to maintain their encoded information intact over time, it is necessary to keep them (most of the existent qubit classes) at very low temperature in dedicated dilution fridges; spin qubits in particular (the type of qubits that this work will focus on) need to be kept at around 2-300mK in most of the technologies available nowadays. Since having millions of big wires coming out of a fridge to control the qubits is nor feasible nor reasonable, it has been
proposed that a big part of the interface electronics is moved from room temperature to cryogenic temperature, close to the qubits.
The readout of a qubit consists in translating its state into a piece of information that can be used for computation in quantum algorithms. In the specific case of spin qubits, the information is encoded in the spin of electrons or quantum states of multiple electrons, when those are subjected to a magnetic field. The weak magnitude of the signal encoding this type of information, together with the temperature at which the system operates result in very strict requirements for power and noise of the integrated circuit.
This work presents a review of the readout process together with the design and simulation of a low frequency readout circuit. Many readout techniques are addressed and pros and cons of each one are discussed before diving into the actual circuit design. The SiGe BiCMOS technology from IHP is analyzed due to its potential for realizing low noise readout circuit. This technology is used in Cadence for simulating and assessing the performance of some proposed readout circuit architectures, namely the Current amplifier, the Voltage amplifier, the Transimpedance amplifier and the Charge amplifier. Eventually, the Voltage amplifier, which shows the more promising results in preliminary simulations, is designed at transistor level and combined with other blocks to realize the whole front-end readout circuit. From the simulation results, it is believed that the circuit can meet the target specification of 10dB SNR and achieve a functional reading at cryogenic temperature with a power consumption lower than 10µW at a speed of 1Ms/s.