A second-order incremental Sigma-Delta Capacitance-to-Digital Converter with auto-zero technique

Abstract

Electronic noses (e-noses) play a vital role in the Internet of Things (IoT), functioning as standalone nodes that collect environmental data such as humidity, temperature, and volatile organic compounds (VOCs). This thesis presents the design of a readout circuit for an existing CMOS capacitive sensor array, utilizing a second-order hybrid (active–passive) sigma-delta ADC.
Unlike conventional sigma-delta converters that process voltage inputs, the proposed ADC directly handles capacitance variations. Environmental changes induce shifts in the sensor array’s capacitance, which are converted into current signals using a switched-capacitor technique. The first integrator is implemented passively, comprising an integration capacitor and the equivalent resistance of the switched-capacitor network. The second integrator adopts an active 𝑔𝑚–C structure to enhance node swing and loop gain.
To suppress 1/f noise originating from the transconductance stage, an auto-zeroing technique is employed. The offset is sampled and stored on two dedicated auto-zero capacitors, effectively canceling its influence. As a result, the contribution of 1/f noise to the final output becomes negligible. The primary objective of this work is to ensure that the system’s performance is fundamentally limited by the input thermal noise, with minimal degradation from the 𝑔𝑚 stage and comparator. Fabricated in NXP’s 140 nm CMOS process, the ADC operates at 100 MHz, achieving an SNR of 82 dB and a bandwidth of 12.2 kHz, while consuming only 46 μW of power. The resulting figure of merit (FoM) is 160 dB.