Cryogenic Control Circuit For Shuttling-based Gate in Germanium Spin Qubit System

Master Thesis (2024)
Author(s)

Y. Zhu (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Contributor(s)

Fabio Sebasatiano โ€“ Mentor (TU Delft - Quantum Circuit Architectures and Technology)

M. Rimbach-Russ โ€“ Graduation committee member (TU Delft - QCD/Rimbach-Russ)

Michiel A.P. Pertijs โ€“ Graduation committee member (TU Delft - Electronic Instrumentation)

Faculty
Electrical Engineering, Mathematics and Computer Science
More Info
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Publication Year
2024
Language
English
Graduation Date
28-08-2024
Awarding Institution
Delft University of Technology
Programme
Electrical Engineering
Faculty
Electrical Engineering, Mathematics and Computer Science
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Abstract

Shuttling-based single qubit gate is an emerging method for qubit manipulation that offers
significant advantages, including the elimination of RF signals, simplicity, and reduced
charge noise. Despite its potential, the development of specific shuttling pulses for quantum
operations and the design of cryogenic circuits to facilitate these pulses are areas that
remain largely unexplored. This gap has led to the focus of my thesis project: designing an
application-specific circuit to implement shuttling gates.
The contributions of this thesis are twofold. The first part begins with an analysis of
the system Hamiltonian, progressing to the development of pulse compilation methods
designed to implement arbitrary quantum gates across a wide range of sample parameter
variations. This section includes extensive quantum dynamics simulations to determine
the necessary specifications for the supporting circuit.
The second part of the thesis details the design of a cryogenic circuit based on imple-
menting a high-precision, wide-range digital-to-time converter using Intel 16nm FinFET
technology. This segment covers the proposed architecture, sub-circuit schematics, and
performance simulations. The subcircuit achieves sub-picosecond resolution and can ex-
tend to a microsecond-level operational range. It also maintains low power consumption,
with common delay circuits consuming only 2.8๐‘š๐‘Š and dedicated delay circuits 44๐œ‡๐‘Š
for each qubit. This efficiency demonstrates the circuitโ€™s potential to control thousands of
shuttling qubits effectively

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