Ultra-Low-power Fully integrated CMOS Real-Time Clock for Autonomous Sensors for Lunar Extreme Temperatures

Master Thesis (2024)
Author(s)

B.W. Xu (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Contributor(s)

F. Sebastiano – Mentor (TU Delft - Quantum Circuit Architectures and Technology)

K. Makinwa – Graduation committee member (TU Delft - Microelectronics)

Chris Verhoeven – Graduation committee member (TU Delft - Electronics)

Faculty
Electrical Engineering, Mathematics and Computer Science
More Info
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Publication Year
2024
Language
English
Graduation Date
15-11-2024
Awarding Institution
Delft University of Technology
Project
['Moonshot']
Programme
['Electrical Engineering']
Faculty
Electrical Engineering, Mathematics and Computer Science
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Abstract

To support the exploration of the Moon, wireless sensor networks could be deployed. However, using a very large number of tiny sensing nodes to collect data in such a harsh environment has many challenges. Integrated circuits are exposed to a wide temperature range (-253 Β°C / +120 Β°C) during the lunar days and nights. To meet the very constrained power budget of an autonomous node, the node time references must consume ultra-low power while maintaining an accurate frequency. To allow accurate operation over the wide target temperature range and be robust to radiations, this thesis proposes to lock the frequency of a frequency locked loop (FLL) to an LC filter. In the FLL, a high-frequency low-power ring oscillator is locked to a separate LC filter to potentially save power with respect of a standard LC oscillator. To further save power, the FLL is heavily duty-cycled and turned on only to calibrate a lower-frequency oscillator to compensate its drift due to noise and environmental changes, thus achieving ultra-low-power dissipation. This thesis explores the design and implementation of the first LC-based FLL by proposing a system architecture, analyzing its limitations and proposing a transistor-level implementation. The resulting time reference, when implemented in TSMC 40-nm process, consumes 773.29πœ‡π‘Š power and achieved an estimated 41.89π‘π‘π‘š/ π‘œπΆ temperature coefficient within an 0.389π‘šπ‘š2 chip area.

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