Addressing the advancement toward large-scale quantum computers, this article presents the first four-level pulse amplitude modulation (PAM4) wireline transmitter (TX) operating at cryogenic temperatures (CTs). With quantum computers scaling up toward thousands of quantum bits (qubits), but having too limited fidelity for robust operation, continuous rounds of quantum error correction (QEC) are necessary. However, QEC requires a large amount of data to be transferred from a cryogenic controller at 4 K to a classical processor at room temperature (RT). To bridge the gap, a high-speed data link between the quantum processor at CT and the classical counterpart at RT is needed. The proposed PAM4 TX architecture integrates a low-power 64:4 serializer structure, a high-speed 4:1 current-mode logic (CML) multiplexer, and a linear 6-bit digital-to-analog converter (DAC). Considering the challenges and benefits of CMOS operating at CTs, the TX architecture and circuitry are designed to exploit the maximum speed, while maintaining sufficient linearity. The fabricated 40-nm CMOS chip achieves a data rate of 40-Gb/s (36-Gb/s), an energy efficiency of 2.46 pJ/b (2.47 pJ/b), and 97.8% (96.6%) ratio of level mismatch (RLM) at CT (RT). While demonstrating an energy efficiency comparable to prior-art TXs in more advanced CMOS nodes at RT, the broad operating temperature of the proposed TX enables the required high-speed wireline link for large-scale quantum computers.

Striving toward a scalable quantum processor, this article presents the first cryo-CMOS quantum bit (qubit) controller targeting color centers in diamond. Color-center qubits enable a modular architecture that allows for the 3-D integration of photonics, cryo-CMOS control electronics, and qubits in the same package. However, performing quantum operations in a scalable manner requires large currents in the driving coils due to low coil-to-qubit coupling. Moreover, active calibration of the qubit Larmor frequency is required to compensate inhomogeneities of the bias magnetic field. To overcome these challenges, this work proposes both a cryo-CMOS alternating current (AC) controller consisting of a class-DE series-resonant driver and a DC current regulator (DC CR) that uses a triode-biased H-bridge for scalable low-power qubit operations. By experimentally validating the cryo-CMOS performance with a nitrogen-vacancy (NV) color-center qubit, the AC controller can drive a Rabi oscillation up to 2.5 MHz with a supply draw of 6.5 mA, and the DC CR can tune the Larmor frequency by ±9 MHz while driving up to ±20 mA in the bias coil. T ^∗ ₂ coherence times up to 5.3μs and single-qubit gate fidelities above 98% are demonstrated with the cryo-CMOS control using Ramsey experiments and gate set tomography (GST), respectively. The results demonstrate the efficacy of the proposed cryo-CMOS chips and enable the development of a modular quantum processor based on color centers.

We realize high-fidelity gates for the two-qubit system formed by NV center. Using gate set tomography, we report gate fidelities exceeding 99%, and analyze the origin of the errors.

Quantum processors based on color centers in diamond are promising candidates for future large-scale quantum computers thanks to their flexible optical interface, (relatively) high operating temperature, and high-fidelity operation. Similar to other quantum-computing platforms, the electrical interface required to control and read out such qubits may limit both the performance of the whole system and its scalability. To address this challenge, this work analyzes the requirements of the electrical interface and investigates how to efficiently implement the electronic controller in a scalable architecture comprising a large number of identical unit cells. Among the different discussed functionalities, a specific focus is devoted to the generation of the static and dynamic magnetic fields driving the electron and nuclear spins, because of their major impact on fidelity and scalability. Following the derived requirements, different system architectures, such as a qubit frequency-multiplexing scheme, are considered to identify the most power efficient approach, especially in the presence of inhomogeneity of the qubit Larmor frequency across the processor. As a result, a non-frequency-multiplexed, 1-mm2 unit-cell architecture is proposed as the optimal solution, able to address up to one electron-spin qubit and 9 nuclear-spin qubits within a 3-mW average power consumption, thus establishing the baseline for the scalable electrical interface for future large-scale color-center quantum computers.

This paper presents an extensive characterization of the low-frequency noise (LFN) at room temperature (RT) and cryogenic temperature (4.2 K) of 40-nm bulk-CMOS transistors. The noise is measured over a wide range of bias conditions and geometries to generate a comprehensive overview of LFN in this technology. While the RT results are in-line with the literature and the foundry models, the cryogenic behavior diverges in many aspects. These deviations include changes with respect to RT in magnitude and bias dependence that are conditional on transistor type and geometry, and even an additional systematic Lorentzian feature that is common among individual devices. Furthermore, we find the scaling of the average LFN with the area and its variability to be similar between RT and 4.2 K, with the cryogenic scaling reported systematically for the first time. The findings suggest that, as no consistent decrease of LFN at lower temperatures is observed while the white noise is reduced, the impact of LFN for precision analog design at cryogenic temperatures gains a more predominant role.

In semiconductor spin quantum bits (qubits), the radio-frequency (RF) gate-based readout is a promising solution for future large-scale integration, as it allows for a fast, frequency-multiplexed readout architecture, enabling multiple qubits to be read out simultaneously. This article introduces a theoretical framework to evaluate the effect of various parameters, such as the readout probe power, readout chain's noise performance, and integration time on the intrinsic readout signal-to-noise ratio, and thus readout fidelity of RF gate-based readout systems. By analyzing the underlying physics of spin qubits during readout, this work proposes a qubit readout model that takes into account the qubit's quantum mechanical properties, providing a way to evaluate the tradeoffs among the aforementioned parameters. The validity of the proposed model is evaluated by comparing the simulation and experimental results. The proposed analytical approach, the developed model, and the experimental results enable designers to optimize the entire readout chain effectively, thus leading to a faster, lower power readout system with integrated cryogenic electronics.

Continuous rounds of quantum error correction (QEC) are essential to achieve faulttolerant quantum computers (QCs). In each QEC cycle, thousands of ancilla quantum bits (qubits) must be read out faster than the qubits' decoherence time (<<T2∗~120μs for spin qubits). To address this urgent need, several CMOS receivers operating at cryogenic temperatures (cryo-CMOS RXs) have recently been introduced for gate-based [1] and RF reflectometry [2] readout of spin qubits, as well as transmons' dispersive readout [3]. However, they have a few shortcomings. First, due to the temperatureindependent shot noise of transistors in nanometer CMOS technology [4], their measured noise temperature (TN) is limited to 40K, thus degrading qubit readout fidelity. Second, due to their large TN, prior art showed either only the electrical performance of their chips by applying a relatively large (i.e., -85dBm [2]) modulated signal directly to the RX input [2,3] or offered limited qubit measurements by exploiting a HEMT amplifier prior to the RX [1]. Those issues hinder future monolithic integration between solid-state qubits and readout electronics. This work advances the prior art by (1) introducing a wideband passive amplification circuit at the RX front-end to minimize the shot noise contribution of the active devices, lowering prior art TN by ~2.7x; (2) demonstrating the RX performance in an RF-reflectometry qubit readout scheme without using off-the-shelf LNA prior to the RX.

Design, simulation, analysis and verification methodologies are crucial for developing electronic circuits and systems at large. Whereas long-standing EDA software is used in the semiconductor technology, there is no counterpart for quantum computing systems yet. Although the quantum computing community started utilizing and adapting some of the already existing EDA tools, for instance, to design quantum processors and control electronics for driving the qubits, or even to solve some quantum computing design tasks, they do not fully use the expertise gained over the last decades in the field of design automation. Current intermediate-scale quantum computers have been designed in an 'adhoc' manner with heterogeneous methods and tools. As we are entering the large-scale era, it is timely and key to further adopt EDA methodologies and software for quantum computing. In this paper, we provide an overview on how full-stack quantum computing systems are being implemented nowadays and discuss which the main challenges are for transitioning from this current scenario to a comprehensive framework encompassing full automated system-wide architecting, design, simulation, verification, and test.

The interface electronics needed for quantum processors require cryogenic CMOS (cryo-CMOS) embedded digital memories covering a wide range of specifications. To identify the optimum architecture for each specific application, this article presents a benchmark from room temperature (RT) down to 4.2 K of custom SRAMs/DRAMs in the same 40-nm CMOS process. To deal with the significant variations in device parameters at cryogenic temperatures, such as the increased threshold voltage, lower subthreshold leakage, and increased variability, the feasibility of different memories at cryogenic temperature is assessed and specific guidelines for cryogenic memory design are drafted. Unlike at RT, the 2T low-threshold-voltage (LVT) DRAM at 4.2 K is up to 2 × more power efficient than both SRAMs for any access rate above 75 kHz since the lower leakage increases the retention time by 40 ,000 × , thus sharply cutting on the refresh power and showing the potential of cryo-CMOS DRAMs in cryogenic applications.

This article presents a family of sub-1-V, fully-CMOS voltage references adopting MOS devices in weak inversion to achieve continuous operation from room temperature (RT) down to cryogenic temperatures. Their accuracy limitations due to curvature, body effect, and mismatch are investigated and experimentally validated. Implemented in 40-nm CMOS, the references show a line regulation better than 2.7%/V from a supply as low as 0.99 V. By applying dynamic element matching (DEM) techniques, a spread of 1.2% (3σ ) from 4.2 to 300 K can be achieved, resulting in a temperature coefficient (TC) of 111 ppm/K. As the first significant statistical characterization extending down to cryogenic temperatures, the results demonstrate the ability of the proposed architectures to work under cryogenic harsh environments, such as space- and quantum-computing applications.

Color-center quantum bits (qubits), such as the Nitrogen-Vacancy center (NV) in diamond, have demonstrated entanglement between remote (>1.3km) qubits and excellent coherence times [1], all while operating at a few Kelvins. Compared to other qubit technologies typically operating at mK temperatures, the higher operating temperature of NVs enables scalable 3D integration with cryo-CMOS control electronics [2], provides significantly more cooling power, and removes the interconnect bottleneck between the qubits and the electronics in prior art [3-5]. Yet, no cryo-CMOS controller for NV-based quantum computers (QC) has been demonstrated.

Cryogenic CMOS (cryo-CMOS) circuits are often hindered by the cryogenic threshold-voltage increase. To mitigate such an increase, a forward body biasing (FBB) technique in bulk CMOS is proposed, which can operate up to the nominal supply without problematic leakage currents, thanks to the larger diode turn-on voltage at cryogenic temperatures. As a result, traditional circuits, such as pass-gates, can operate down to 4.2 K, and their performance is augmented, e.g., digital circuits speeding up by 1.62× or lowering their energy per transition and energy-delay product by 4.24× and 2.33× , respectively. Unlike back biasing in FD-SOI, here all FBB voltages remain within the supplies, hence enabling on-chip and device-specific biasing. The proposed FBB technique thus represents a valuable design tool for bulk cryo-CMOS circuits.

This paper presents a floating inverter amplifier (FIA) that performs high-linearity amplification and sampling while driving a 2<inline-formula> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> time-interleaved (TI) SAR ADC, operating from room temperature (RT) down to 4.2 K. The power-efficient FIA samples the continuous-time input signal by windowed integration, thus avoiding the traditional sample-and-hold. Cascode switching, a floating supply and accurate pulse-width timing calibration enable high-speed operation and interleaving. In addition, by exploiting the behavior of CMOS devices at cryogenic temperatures, forward-body-biasing (FBB) is pushed well beyond what is possible at RT to ensure performance down to 4.2 K, and its impact on the performance of cryogenic circuits is analyzed. The resulting ADC, implemented in 40-nm bulk CMOS and including the FIA driver, achieves SNDR<inline-formula> <tex-math notation="LaTeX">$=$</tex-math> </inline-formula>38.7 dB (38.2 dB), SFDR<inline-formula> <tex-math notation="LaTeX">$&gt;$</tex-math> </inline-formula>50 dB (<inline-formula> <tex-math notation="LaTeX">$&gt;$</tex-math> </inline-formula>50 dB), and FOMW<inline-formula> <tex-math notation="LaTeX">$=$</tex-math> </inline-formula>25.4 fJ/conv-step (31.3 fJ/conv-step) with Nyquist-rate input at 1.0 GS/s (0.9 GS/s) at 4.2 K (RT), respectively.

Quantum computers process information stored in quantum bits (qubits), which must be controlled and read out by a traditional electronic interface. Co-designing and cooptimizing such a quantum-classical complex system requires efficient simulators to emulate the qubits and their interaction with classical electronics. For spin-qubit readout, a single electron transistor (SET) is often employed. To build a toolset that can co-simulate the spin qubit system with the classical control and readout interface, a compact and efficient SET model is needed. This paper presents a new compact empirical SET model based on state-of-the-art SET measurement and extracted by a custom function-fitting python program. Within the target source-drain voltage range of ±1000μV , the model is accurate for circuit (SPICE) simulation. Furthermore, the empirical model is represented by a set of equations that enables instantaneous output response requiring a negligible simulation time. With this new SET model, a quantum-electronics co-simulator such as SPINE can now be enhanced to simulate the readout in addition to the control circuits of spin qubits, thus enabling the design of the complete integrated circuit (IC) required for large-scale quantum computers.

State-of-the-art quantum computers already comprise hundreds of cryogenic quantum bits (qubits), and prototypes with over 10k qubits are currently being developed. Such large-scale systems require local cryogenic electronics for qubit control and readout, leaving the digital controllers for algorithm execution and quantum error correction (QEC) at room temperature due to the limited cryogenic cooling budget. The entire process, including qubit readout, data transmission, QEC, and algorithm execution, should be completed well within the qubit decoherence time, thus requiring a low-power high-speed communication link between the cryogenic quantum processor and classical processor located at room temperature. To this end, this paper presents the first cryo-CMOS high-speed 4-level pulse amplitude modulation (PAM4) wireline transmitter. Thanks to a power-efficient serializing architecture driving a 6-bit digital-to-analog converter (DAC), the 40-nm CMOS chip achieves a data rate of 40 Gb/s PAM4 with an efficiency of 2.46pJ/b and a ratio of level mismatch (RLM) of 97.8% at 4.2 K. While demonstrating an energy efficiency comparable to state-of-the-art transmitters in more advanced CMOS nodes, the extremely wide temperature operating range (4.2 K - 300 K) will enable future large-scale quantum computers.

Quantum computing is poised to solve practically useful problems which are computationally intractable for classical supercomputers. However, the current generation of quantum computers are limited by errors that may only partially be mitigated by developing higher-quality qubits. Quantum error correction (QEC) will thus be necessary to ensure fault tolerance. QEC protects the logical information by cyclically measuring syndrome information about the errors. An essential part of QEC is the decoder, which uses the syndrome to compute the likely effect of the errors on the logical degrees of freedom and provide a tentative correction. The decoder must be accurate, fast enough to keep pace with the QEC cycle (e.g. on a microsecond timescale for superconducting qubits) and with hard real-time system integration to support logical operations. As such, real-time decoding is essential to realize fault-tolerant quantum computing and to achieve quantum advantage. In this work, we highlight some of the key challenges facing the implementation of real-time decoders while providing a succinct summary of the progress to-date. Furthermore, we lay out our perspective for the future development and provide a possible roadmap for the field of real-time decoding in the next few years. As the quantum hardware is anticipated to scale up, this perspective article will provide a guidance for researchers, focusing on the most pressing issues in real-time decoding and facilitating the development of solutions across quantum, nano and computer science.

Over the past decade, significant progress in quantum technologies has been made, and hence, engineering of these systems has become an important research area. Many researchers have become interested in studying ways in which classical integrated circuits can be used to complement quantum mechanical systems, enabling more compact, performant, and/or extensible systems than would be otherwise feasible. In this article - written by a consortium of early contributors to the field - we provide a review of some of the early integrated circuits for the quantum information sciences. Complementary metal - oxide semiconductor (CMOS) and bipolar CMOS (BiCMOS) integrated circuits for nuclear magnetic resonance, nitrogen-vacancy-based magnetometry, trapped-ion-based quantum computing, superconductor-based quantum computing, and quantum-dot-based quantum computing are described. In each case, the basic technological requirements are presented before describing proof-of-concept integrated circuits. We conclude by summarizing some of the many open research areas in the quantum information sciences for CMOS designers.

In this contribution, we describe the modeling approaches and the characterization procedures used to develop accurate standard models for cryogenic, probe-level, calibrations substrates.The key electrical and mechanical parameters of the impedance terminations and the lines used in commercially available impedance standard substrates are first characterized versus temperature. After, these component are simulated using 2.5D EM solvers including their mechanical variation when exposed to cryogenic temperatures, to extract their nominal response at 7 Kelvin. The quality of the resulting calibrations at cryogenic is evaluated first using independent CPW lines on the calibration substrates and then by measuring the response of a transformer-based resonator realized on a Si-based technology.Ambient temperature models are used as a comparison, to highlight the accuracy improvement that can be achieved employing optimized Cryo-EM based models.

This article presents the first cryogenic phase-locked loop (PLL) operating at 4.2 K. The PLL is designed for the control system of scalable quantum computers. The specifications of PLL are derived from the required control fidelity for a single-qubit operation. By considering the benefits and challenges of cryogenic operation, a dedicated analog PLL structure is used so as to maintain high performance from 300 to 4.2 K. The PLL incorporates a dynamic-amplifier-based charge-domain sub-sampling phase detector (PD), which simultaneously achieves low phase noise (PN) and low reference spur, thanks to its high phase-detection gain and minimized periodic disturbances on the voltage-controlled oscillator (VCO) control. Fabricated in a 40-nm CMOS process, the PLL achieves <inline-formula> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula>78.4-dBc reference spur, 75-fs rms jitter, and 4-mW power consumption at 300 K when generating a 10-GHz carrier, leading to a <inline-formula> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula>256.5-dB jitter-power FOM. At 4.2 K, the PLL synthesizes 9.4-to 11.6-GHz tones with an rms jitter of 37 fs and a reference spur of <inline-formula> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula>69 dBc while consuming 2.7 mW at 10 GHz.