Two devices, a SiGe BiCMOS MOSFET and a SiGe HBT, were characterized through on-wafer measurements in the 220–500 GHz range. The results showed that the PDK model of the MOSFET did not accurately represent the device. Conventional open–short de-embedding was found to lose accuracy at sub-THz frequencies due to its inherent lumped-element approximation. To address this limitation, an improved de-embedding method was developed by estimating a correction matrix A′ using transmission-line equivalent circuits, achieving up to 15.6 dB improvement in S11 and S22 for an HBT interconnect in simulation compared to the classical approach. The characterized MOSFET was used to simulate the integrated chopper transmissivity, which closely matched over-the-air measurements. The HBT characterization showed better agreement with the PDK, but the higher characterized capacitance resulted in reduced chopper performance.

This thesis presents the design of a bidirectional low-dropout voltage regulator(LDO) for CMOS drivers in a 3.5 GHz digital transmitter (DTX). A tightly regulated 0.9V mid-rail supply is required to ensure short rise/fall times and maintain Adjacent channel leakage ratio(ACLR) performance. Regulator specifications were derived by porting the LDMOS driver to a 22 nm FDSOI process and characterizing its current demand across PVT corners, requiring up to 2.9 mA sourcing and 1.9 mA sinking with < ±1.5 mV voltage deviation. A complementary push–pull architecture with a folded-cascode error amplifier, super-source-follower buffers, and differentiator-based compensation was implemented to achieve low output impedance without excessive on-chip capacitance. Simulations confirm < 573 μA quiescent current, phase margin > 45°, and acceptable ACLR performance, validating the design for integration in CMOS/LDMOS DTX systems.

After reviewing fundamental architectural concepts and surveying the current landscape of state-of-the-art digital transmitters, this thesis introduces two novel techniques aimed at improving efficiency. The first contribution is a Class-E power amplifier featuring a reconfigurable output matching network, designed to enhance drain efficiency during power back-off. Building upon insights from this design, the second contribution addresses its limitations by proposing a hybrid transmitter architecture that overcomes the efficiency bottlenecks associated with high-frequency digital operation. The thesis concludes with key findings and formulates open research questions to guide future work in the field.

As classical computing paradigms approach their physical limits, quantum computing has emerged as a promising solution capable of solving certain complex problems with substantial speedup. However, before quantum computers can be deployed in real-world situations, they must be able to scale up to thousands of qubits with high fidelity while maintaining the ability to accurately and precisely control each qubit. This requires a part of the digital control logic placed close to each qubit that orchestrates the control signals sent to each qubit -- the local controller. This thesis focuses on the design and implementation of this local controller for operations on diamond qubits, building on top of an existing control architecture, from specifying the design requirements to actual hardware implementation and verification.

Multiple contributions are made in this thesis towards realizing a fully functional local controller design. The required functionalities for full support of all quantum operations are identified. Based on these functionalities, the designs of the new components and microinstructions are proposed. These designs are implemented as microcode and circuit architectures. In this process, a control sequence and relevant architecture for entanglement generation between color centers are proposed and implemented. An improved communication scheme with the network of local controllers has also been implemented to meet functional requirements and facilitate performance improvements. The new implementations are verified and prototyped on an FPGA performing actual quantum operations, demonstrating that the local controller is capable of performing all types of quantum operations with sufficient accuracy and precision, integrating seamlessly with peripheral components in the quantum control layer.

The work of this thesis represents a major step forward in the microarchitectural stack of a diamond quantum computer, paving the way toward the realization of large-scale quantum computing capable of addressing practical, real-world problems.

This thesis presents the design of a low-power digital-input Class-D amplifier for battery-powered headphone applications. This Class-D amplifier operates with pulse density modulation (PDM) at a 12.288 MHz sampling frequency with three-level and dynamic hysteresis operation in the power stage to enhance the efficiency across a wide output power range. A three-level resistive digital-to-analog converter (RDAC) with reset-then open control strategy is used to improve the dynamic range while maintaining good linearity. This design is implemented in 16 nm FinFET technology. With a 1.8 V supply and a 40-Ω + 4-mH speaker load, the Class-D amplifier achieves a dynamic range (DR) of 116.7 dB and an idle power consumption of 1.71 mW. At the 23 mW maximum output power, it achieves 88.7% efficiency and a peak total harmonic distortion (THD) of -105.7 dB.

Integrated temperature sensors are widely used in various applications, including thermal monitoring, medical devices, and voltage/frequency references. An emerging class of temperature sensors operates by measuring the thermal diffusivity (TD) of silicon. This can be done by measuring the time it takes for heat to diffuse between a heater and a relative temperature sensor, both implemented in a silicon substrate. The key advantage of such TD-based sensors is that their accuracy improves linearly with lithographic precision.

Increasing the length of the heat path and/or moving to a more advanced technology node will enhance measurement accuracy. However, since silicon is an excellent heat conductor, the output of such sensors is at the millivolt level, which makes the design of accurate readout circuitry quite challenging.

In this work, an accurate readout circuit was designed for TD-based sensors realized in a 65nm process. It consists of a low-noise pre-amplifier, followed by a Sigma-Delta ADC. Based on simulation results, the designed circuit achieves a 23 mK (3σ) inaccuracy at 27◦C, which is negligible compared to the expected inaccuracy of the TD-based sensors.

This thesis details the design of a high-speed RF delay locked loop(DLL). A new proposed phase detector architecture, coined the mixing phase detector, allows for phase detection at high frequencies, resulting in multiphase generation at these higher frequencies with a DLL. The mixing phase detector modulates the high frequency signal to DC, allowing for elementary circuits to be used that do not need high frequency capabilities. The mixing phase detector has been designed, entirely laid out, and will be taped out shortly, with which simulations have been performed and have been compared with the state-of-the-art. The simulated results, show the possibility of generating eight phases accurately at 11.1 GHz, which would be higher than the state-of-the-art.

Quadrature clocks have been widely used in both wireless and wireline communication systems. This Master’s project presents a quadrature clock generator operating in the 10 GHz to 20 GHz range, specifically tailored for quantum computing applications. The design utilizes delay lines to generate quadrature clocks, ensuring low phase noise. To control the delay of these lines, the delay difference is extracted by down-converting the high-frequency signal (10-20 GHz) to a baseband frequency (50 MHz) while retaining the phase difference. Quadrature errors are detected using a tunable delay line and a bang-bang phase detector, resulting in a design that is immune to static delay variations between the two delay extraction paths and is power efficient.

In the past several decades, tremendous progress has been made in physics and engineering towards realize practical quantum computers. Several small-scale systems have already been demonstrated which utilize separate, off-the-shelf hardware components to directly control qubits. However, as higher-quality qubits continue to spur the development of larger-scale systems capable of performing complex computations, it is becoming increasingly important to consider how control architectures should be adapted to keep pace. This motivates the design of a scalable control architecture capable of dynamically orchestrating quantum programs on a large number of qubits while maintaining the stringent requirements imposed by qubit coherence times and operation in dilution refrigerators.

In this thesis, several contributions are made towards realizing a control architecture for large-scale quantum computing systems based on distributed Nitrogen-vacancy (NV) centers in diamond. A configurable design is presented which significantly increases system throughput by parallelizing execution of instructions performed on separate distributed nodes. A detailed analysis of the dependencies between instructions in quantum programs at an algorithmic level is also used to develop an heuristic function for evaluating the performance of different hardware designs. Furthermore, the demand for increased complexity of computations is addressed by a microarchitectural design which translates high-level quantum instructions into a set of signals used to configure special-purpose signal generators. Taken together, these microarchitectural components enable highly-efficient generation of signals for performing arbitrary single-qubit rotation gates, a key step towards achieving universal quantum computation.

Additionally, detailed evaluations of the control architecture enhancements are provided. For example, run time analysis is performed on a set of benchmark quantum algorithms to show the significant speedup capabilities and performance tradeoffs of the control architecture's parallel execution model. Moreover, the successful integration of the control architecture with the pre-existing signal generators is verified by executing parameterized microinstructions which configure the signal generators to produce amplitude-modulated, phase-coherent microwave and radio-frequency signals. Finally, the full system functionality is verified using several microprograms which each implement higher-level quantum instructions for single-qubit rotation gates. These demonstrations bridge the end-to-end connection between quantum algorithms and physically-realizable quantum gates in hardware.

Efficiency in handling instructions within compilation and control processes is essential for scalability and fault-tolerant quantum computation. To mitigate the limited bandwidth for transmission of instructions and energy bottlenecks in cryogenic control architectures, this thesis aims to develop a compressed representation of quantum circuits. To achieve this goal, we study the concepts of algorithmic information theory and resource theory of computation. We focus on description complexity and establish compression as a useful estimate of algorithmic description complexity. With this motivation, we develop a generalized framework for the synthesis of quantum unitaries into a set of native gates and present a Huffman-encoded representation of the instruction stream that has a short code dictionary and offers a 60% compression over binary encoded representations. The developed framework offers 2 major contributions: an energy-efficient encoded representation of the quantum instruction stream and an estimate of the description complexity for quantum circuits. It qualifies as a successful algorithmic approach towards optimizing the QISA and aids the discovery of high-level quantum programming constructs.

This thesis describes the implementation of a phase-domain readout system for a thermal-diffusivity (TD) based temperature sensor. Such sensors measure the phase shift of an electro-thermal filter (ETF), which exhibits a near-linear dependency on absolute temperature. The phase shift is measured by a phase-domain delta-sigma modulator (PD-DSM). Although ETFs can be very accurate, their readout circuitry often constrains overall performance. A notable concern is their offset, which is usually much larger than the ETF’s output signal and may cause the PD-DSM to clip. In this work, this issue is addressed by a hybrid offset-reduction strategy. The PD-DSM itself is designed to achieve a temperature inaccuracy of 0.04°C.
The design was fabricated using TSMC 180nm CMOS technology. Due to a design error, the PD-DSM did not achieve the targeted accuracy. Nonetheless, the hybrid offset cancellation scheme works as intended, demonstrating efficacy by effectively mitigating residual offset to sub-µV levels across temperature ranges extending up to 180°C.

"Quantum optimal control is a rapidly growing field with diverse methods and applications. In this work, the possibility of using quantum optimal control techniques to co-optimize the energetic cost and the process fidelity of a quantum unitary gate is investigated. The theoretical definition and quantization of quantum unitary gates, as well as the relationship between the process fidelity and the energetic cost of a quantum unitary gate are explored. Two different quantum optimal control methods to co-optimize both fidelity and energetic cost, i.e., the Gradient Ascent Pulse Engineering method and model-free Deep Reinforcement Learning are investigated. The performance of both quantum optimal control techniques in the presence of noise is probed. We find that the energetic cost of a quantum unitary gate can be quantized by integrating the control pulses and norm of the corresponding Hamiltonian operators over the total time duration of the unitary, and for single qubit gates by calculating the arc length of the quantum unitary gate on the Bloch sphere. A Pareto optimal front between the process fidelity and the energetic cost of a quantum gate is identified, where a lower energetic cost yields an inherently lower process fidelity. A python package called ”EUQOC” (Energy Efficient Universal Quantum Optimal Control) has been created to implement energy optimal quantum gate synthesis, both with the Energy Optimal Gradient Ascent Pulse Engineering (EO-GRAPE) method and by model-free Deep Reinforcement Learning. It is found that the EO-GRAPE method performs better than the reinforcement learning methods, for all noise settings and neural network sizes. For future work, the optimization problem could be translated to the frequency domain to increase the computational efficiency. Furthermore, the relationship between information and energy can be investigated by looking at the complexity of the pulse or the decomposition of the quantum unitary gate."

The escalating demand for higher data rates in modern communication networks are pushing more transmitters and receivers to use a modulation technique with more spectral efficiency, like pulse amplitude modulation 4-level (PAM-4).

On the receiver side, phase detection for PAM-4 has proven to be difficult with most receivers using phase detection for non return to zero (NRZ) data. This neglects most transitions and thus some phase information is lost. This results in low bandwidth and jitter tolerance, which is a problem in noisy communication systems where it will lead to a high bit error rate (BER).

This thesis explores an integrated PAM-4 clock and data recovery (CDR) circuit utilizing a novel PAM-4 bang bang phase detector (BBPD) considering all data transitions. A digital oscillator with variable gain is used in order to achieve high jitter tolerance as-well as low jitter generation. at 24Gb/s the CDR consumes 8mW and generates 487fs of jitter. and has a 1UI at 30MHz.

Thermoelectric generators (TEGs) are critical in environments where alternative energy harvesting methods are necessary, such as space exploration. This thesis investigates using a two-dimensional hole gas (2DHG) as a p-type material within a Gallium Nitride (GaN) based TEG. This study focuses on determining the thermoelectric performance of the 2DHG by measuring the Seebeck coefficient, electrical conductivity, and power factor for extremely cold environments.

This work introduces a novel simulation method used to evaluate different structures to find the optimal hole densities for maximizing the power factor (PF) of the 2DHG. A structure was realized, and its thermoelectric properties were experimentally assessed. Key results, including a Seebeck coefficient of 100 − 200 μV /∆K, a sheet resistance of 70 − 120 kΩ , and a resulting Power Factor (PF) of 60 − 100 μW m−1K−2, are measured over an extremely low-temperature range of 50 - 300 Kelvin and discussed for future applications.

These results demonstrate that GaN-based TEGs can significantly broaden the temperature range and improve the performance of TEGs in extreme conditions. These findings pave the way for more efficient thermoelectric systems, with potential applications in aerospace, deep-space missions, and other challenging environments.

In this thesis, a low-power, high-accuracy BJT-based temperature sensor is proposed, which consists of two main parts: a BJT-based dual-mode front-end (DMFE) and a tracking Delta-Sigma-Modulator (DSM). The front-end employs vertical PNP transistors, which, compared to NPNs, exhibit fewer non-idealities when biased at nA-level currents. The proposed DMFE generates accurate proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) voltages, while only consuming half the power of a conventional front-end. The temperature dependent ratio of these voltages is then digitized by an energy-efficient tracking DSM. The prototype sensor was fabricated in a 0.18µm CMOS process and has an active area of 0.228mm2. Measurement results show that the sensor achieves an inaccuracy of ±0.15°C (3σ) over the industrial temperature range (-45°C to 85°C) after 1-point temperature calibration, which corresponds to a relative inaccuracy of 0.3%. It also achieves a 32mK resolution in 100ms, while consuming only 130nW. Its low power consumption, accuracy, and resolution make it suitable for IoT applications.

This work describes a fully digital transmitter (DTX) for 5G mMIMO base stations that combines the strengths of high-speed digital CMOS with the high-power capabilities of a Monolithic Microwave Integrated Circuit (MMIC) high-voltage technology. This technology platform offers high integration and scalability for implementing Radio Frequency Digital-to-Analog Converters (RF-DACs). To facilitate the digital operation of the gate-segmented output power stage, a custom VT-shifted LDMOS technology has been utilized. The relatively high output capacitance of the LDMOS devices makes digital class-C operation the preferred class of operation to achieve high efficiency with good linearity metrics for the digital power amplifier (DPA). In this work, we analyze this operation, assuming a trapezoidal-shaped current profile, which allows investigation of the impact of the non-zero rise and fall times on the theoretical (normalized) output power and drain efficiency.
To drive the gate segments in this custom VT LDMOS technology with a gate-to-source voltage (VGS) swing of 2.2 V, a driver is proposed comprising: inverter chains, a level shifter, and a high-voltage output buffer. This driver is fully digital and can be implemented using thin-oxide bulk CMOS devices whose VDD is limited to 1.1 V. A model of the DTX comprising only the drivers and DPA at the circuit level is created in ADS to evaluate the output power, drain efficiency, and system efficiency. The DTX is simulated at 3.5 GHz full power and achieves an output power of 19.79 W/23.43 W, a drain efficiency of 67.28%/59.22%, and a system efficiency of 60.34%/54.48% with a non-empirical and empirical model of LDMOS, respectively. Rise and fall times of around 20% of the RF cycle (tr = tf = 0.2/fc) are found to be the most suitable in terms of power consumption and system efficiency.

The goal of this thesis is expanding quantum algorithm datasets to enhance our capability to benchmark quantum systems and to open up possibilities for using machine learning techniques in quantum circuit mapping. Both of these areas are currently hindered by the lack of a wide range of useful quantum algorithms. To solve this problem, KetGPT is presented, a model that uses the revolutionary transformer machine learning architecture to generate synthetic, yet realistic looking, quantum circuits. By visual inspection, KetGPT generated circuits are easily distinguishable from random circuits, and show desirable qualities such as structure and human-like programming factors including applying gates in the order of ascending qubits. Consequently, they might be more suitable for certain tasks like benchmarking and training a reinforcement learning compiler. In an attempt to quantify the quality of circuits generated by KetGPT, a separate transformer classifier model was trained on the task of classifying the synthetic circuits generated by KetGPT as either real circuits, or as random circuits. However, although this classifier might capture realistic features of quantum circuits, the classifier has not been unambiguously proven to be reliable, and can therefore not be used as a standalone tool to determine the quality of KetGPT generated quantum circuits. Nevertheless, KetGPT and the transformer classifier are novel, promising approaches in an attempt to expand quantum algorithm datasets.

Receivers for millimeter-wave (mm-wave) 5G, with the ability to detect a low-power desired signal, in the vicinity of large power blockers, require highly linear circuitry with a large power consumption. Suppressing the out-of-band blockers reduces this power consumption. N-path filters (NPFs) have recently been used to reject interferers in adjacent channels, by using a tunable center frequency. The state-of-the-art NPFs at mm-wave, however, only have a limited attenuation or use a large chip area. In this thesis, a fourth-order NPF is designed for 26-30 GHz. The implemented filter combines two frequency-shifted NPFs to create a flat in-band response and a steep roll-off, without the use of a large passive baseband filter. A rejection of 14 dB in the center of the first adjacent channel is obtained. This increases up to 24 dB at far-out-of-band frequencies. The noise figure of 10-12 dB is the lowest of the state-of-the-art, due to the added low-noise amplifier (LNA) in front of the filter. Despite this LNA, the designed filter achieves a comparable power consumption (40 mW) and smaller area (0.2-0.3 µm) than the state-of-the-art. The filter designed in this thesis is the first reported active N-path filter at mm-wave. The bandwidth is among the smallest reported, while the estimated area is lower than the state-of-the-art.