Transmitter Architectures for Wireless Applications
V. CHONDRORRIZOS (TU Delft - Electrical Engineering, Mathematics and Computer Science)
Morteza Alavi – Mentor (TU Delft - Electronics)
F. Sebasatiano – Graduation committee member (QCD/Sebastiano Lab)
M. Spirito – Graduation committee member (TU Delft - Electronics)
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Abstract
After reviewing fundamental architectural concepts and surveying the current landscape of state-of-the-art digital transmitters, this thesis introduces two novel techniques aimed at improving efficiency. The first contribution is a Class-E power amplifier featuring a reconfigurable output matching network, designed to enhance drain efficiency during power back-off. Building upon insights from this design, the second contribution addresses its limitations by proposing a hybrid transmitter architecture that overcomes the efficiency bottlenecks associated with high-frequency digital operation. The thesis concludes with key findings and formulates open research questions to guide future work in the field.
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File under embargo until 28-08-2027