Multi-bit IDAC input Class D Amplifier

Master thesis (2023)

Authors

M. Zhang Electrical Engineering, Mathematics and Computer Science

Contributors

Q. Fan Electronic Components, Technology and Materials - EEMCS (supervisor 1)
T.M. Lopes Marta da Costa Bio-Electronics - EEMCS (supervisor 2)
Marco Berkhout Goodix Technology (supervisor 2)
Faculty
Electrical Engineering, Mathematics and Computer Science
Copyright: © 2023 Mingshuang Zhang
Class-D amplifier Mismatch shaping Current-steering DAC THD+N DR
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Published Date

12-12-2023

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Abstract

Class D amplifiers (CDA) have been used considerably in audio applications due to their high-efficiency behavior. Compared to standalone analog input CDAs, digital input CDAs are less sensitive to electromagnetic interference (EMI), which is preferred in automotive applications. For digital input CDAs, multi-bit current-steering DACs using tri-level units offer high dynamic range (DR) compared with other types of DAC. The main challenge in designing low total harmonic distortion plus noise (THD+N) and high DR IDAC lies in noise, mismatch, and ISI reduction. In this project, a new ISI resilient dynamic element matching technique is developed for mismatch shaping and ISI reduction in IDAC.