Multi-bit IDAC input Class D Amplifier

Master Thesis (2023)
Author(s)

M. Zhang (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Contributor(s)

Q. Fan – Mentor (TU Delft - Electronic Components, Technology and Materials)

Tiago L. Costa – Graduation committee member (TU Delft - Bio-Electronics)

Marco Berkhout – Graduation committee member (Goodix Technology)

Faculty
Electrical Engineering, Mathematics and Computer Science
Copyright
© 2023 Mingshuang Zhang
More Info
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Publication Year
2023
Language
English
Copyright
© 2023 Mingshuang Zhang
Graduation Date
12-12-2023
Awarding Institution
Delft University of Technology
Programme
['Electrical Engineering']
Faculty
Electrical Engineering, Mathematics and Computer Science
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Abstract

Class D amplifiers (CDA) have been used considerably in audio applications due to their high-efficiency behavior. Compared to standalone analog input CDAs, digital input CDAs are less sensitive to electromagnetic interference (EMI), which is preferred in automotive applications. For digital input CDAs, multi-bit current-steering DACs using tri-level units offer high dynamic range (DR) compared with other types of DAC. The main challenge in designing low total harmonic distortion plus noise (THD+N) and high DR IDAC lies in noise, mismatch, and ISI reduction. In this project, a new ISI resilient dynamic element matching technique is developed for mismatch shaping and ISI reduction in IDAC.

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File under embargo until 12-12-2025