Text-to-speech (TTS) systems have achieved substantial improvements in quality with the use of neural architectures. Despite these quality improvements, they remain computationally intensive, which limits their deployment on low-power devices. This thesis explores whether a custom hardware accelerator can improve the efficiency of end-to-end TTS inference while maintaining or improving synthesis quality.

A phoneme-to-mel model based on EfficientSpeech is adapted with hardware-aware modifications, such as the replacement of expensive normalisation layers and simplification of activations. These modifications reduce the computational complexity while improving synthesis quality compared to the baseline model. The HiFi-GAN vocoder is optimised by reducing its model size from 920k to 296k parameters, while maintaining a fair quality. Combined, the complete TTS pipeline is reduced from 1.2M parameters to 562K, demonstrating that substantial reductions in both model size and complexity are achievable without sacrificing the synthesis quality.

A custom instruction set and hardware accelerator are designed to support the essential operations used in TTS inference, which include matrix operations, one-dimensional convolutions, and activation functions. The accelerator was synthesised and implemented on an FPGA using an out-of-context mode, achieving a post-implementation clock period of 4.182 ns, while reporting a power consumption of 1.569 W. The reported power consumption is approximately 9.9 times lower than the used baseline GPU system.

An end-to-end TTS inference accelerator is successfully implemented and verified, achieving a consistent real-time factor (RTF) of approximately 0.156 over varying input lengths, confirming real-time inference capability. For the longest test input of 31 phonemes, the accelerator uses 11.3 times less energy than the baseline system, despite the slightly higher RTF compared to the baseline’s 0.172. For shorter inputs, the energy efficiency improves further, with the accelerator consuming over 50 times less energy for a 4-phoneme test case.

This work demonstrates that dedicated hardware accelerators combined with hardware-aware model optimisations can significantly improve the efficiency of real-time neural TTS, enabling deployment on low-power devices such as embedded systems and battery-powered platforms that typically have strict power budgets and cannot rely on continuous mains power.

Audio samples of the optimised TTS models can be found at a demo page, and the hardware accelerator implementation is available open-source at the specified repository.

CMOS Hall sensors consist of current-biased n-well plates that output magnetic-field dependent voltages. Offsets due to n-well inhomogeneity can then be suppressed by the spinning-current technique, which involves periodically rotating the direction of the biasing current and averaging the resulting output voltages. However, its effectiveness is limited by the JFET effect, which refers to the formation of a depletion region between the n-well and the p-type substrate due to the voltage drop across the n-well. This depletion region modulates the n-well resistance, and so is also a source of residual offset.

In this work, a CMOS Hall sensor is reported which employs voltage biasing and reads out the short-circuit Hall current. Compared to current biasing, this stabilizes the voltage drop across the n-well and significantly reduces the offset due to the JFET effect. Implemented in a standard 180nm CMOS process, the resulting sensor achieves a 3σ offset of 1.1μT with a noise floor of 60nT/√Hz. Compared to the state-of-the-art, these results represent a 3x reduction in offset, and a 5x improvement in resolution.

With the increasing requirements of the semiconductor industry, ASML lithographic machines, essential for chip manufacturing, are becoming more complex. Consequently, the mains distribution system, a crucial part of these machines, is increasingly vulnerable to short circuit (SC) faults due to the growing number of system components. SC assessment of this system in compliance with international standards is vital as they are utilized by companies worldwide.

This thesis provides a standardized assessment method for industrial mains distribution system that complies with international standards. The assessment method includes the determination of available SC current and overall short circuit current rating (SCCR) and is implemented as a Matlab tool. Additionally, this thesis explores ways to increase the SCCR of the system by improving protection and limiting current considering current-limiting alternating current circuit breakers and various direct current circuit breaker (DCCB) technologies, including fault current limiters. Finally, the assessment results are validated through the physical testing results of a branch circuit within the ASML mains distribution system.

With the rising demand for high-bandwidth, high-resolution current sensors, commonly used Hall-effect devices fall short due to their relatively high wide-band noise. The coil-Hall hybrid architecture addresses this issue by combining the Hall plate with a pick-up coil, known for its high SNR at high frequencies. This CMOS-compatible architecture achieves excellent noise and bandwidth performance while maintaining the ability to sense DC signals. However, this performance comes at the cost of increased complexity in combining, calibrating, and stabilizing the two distinct signal paths. This thesis thoroughly investigates the various challenges and trade-offs associated with this architecture and provides a comprehensive overview of potential system solutions. Additionally, the insights gained were used to design a prototype chip for SystematIC Design B.V. Seeking to reduce complexity, this led to the invention of a new system architecture. This new architecture effectively overcomes several challenging trade-offs that have hindered existing designs until now and is considered a promising approach for achieving even better performance in the future.

High-voltage pulse train excitation for ultrasonic transducers offers exceptional signal-to-noise ratio (SNR) and enables the possibility of beamforming. Conventional high-voltage pulses cannot be directly generated from low-voltage batteries without a high-voltage source, requiring conversion to high-voltage DC before being shaped into pulses. Recent advancements in resonant pulser circuit architectures have made it feasible to convert low-voltage battery power directly into high-voltage pulses. However, these designs are limited to producing a single half-sine pulse. This work proposes a novel circuit architecture based on a 180nm BCD process, aiming to further enhance the performance of resonant pulsers and enable the generation of pulse trains.

The increasing complexity of Integrated Circuits (ICs) and stringent quality requirements in industries like automotive have contributed to increasing test development time. Virtual testing methodologies, such as AMS-VT, can be used for pre-silicon debugging of test programs, optimizing the test development process. However, AMS-VT has shown limitations in their usage due to the absence of accurate loadboard models, especially in capturing site-to-site variations. To address the lack of an accurate loadboard model for pre-silicon debugging, this research proposes a framework for generating an accurate loadboard model by integrating parasitic effects and possible reflections under real-world conditions.

The proposed framework consists of three main stages. The first stage is an automated netlist generation phase, during which an ideal single-site netlist is created from a multisite loadboard schematic. The ideal netlist is generated considering the AMS-VT environment so that it can be seamlessly integrated into the current virtual testing environment. In the next stage, Cadence PowerSI, which is an Electronic design automation (EDA) tool for parasitic extraction, is automated to extract the parasitics (R, L, G, and C) for all the channels included in the ideal netlist. Finally, in the last stage, a methodology is developed to integrate the parasitics and reflection due to impedance mismatch in the ideal netlist. To improve the accuracy, a static model of the relay was developed that considers its characteristics, such as on-state resistance and off-state current leakage. All these stages are then automated and combined to create a framework that can effectively generate an accurate loadboard netlist that predicts site-to-site variations.

The framework is then validated, with each stage verified independently. The generated ideal single-site netlist was verified against a golden simulation. This verification displayed that the functionality of the generated netlist was accurate and could integrate with AMS-VT seamlessly. The parasitics extracted from PowerSI were validated using a test Printed Circuit Board (PCB) with multiple configurations. This showed that the simulation results using extracted parasitics were within 1% error compared to the IR drop analysis. The relay model was also validated by comparing it with its datasheet, proving that the model accurately considered the physical characteristics. The third stage was then validated by comparing it with PSpice simulations, demonstrating that the model's results were accurate, with the maximum error being below 1.6% for multiple voltages and frequencies. The complete framework was then validated against a physical loadboard, showing maximum errors of less than 2% across all sites and improved timing accuracy for pulse width, reducing it to 0.41% for the proposed framework from 1.6% for the previous methodology. This validation proved that the loadboard generated by the framework accurately modelled parasitics and reflections. The model also accurately accounted for temperature variations, demonstrating its effectiveness in changing operating conditions. By introducing this framework to generate an accurate loadboard model, this research enables a virtual testing environment for faster and more reliable test development, reducing the time-to-market for semiconductor products.

Voltage references are an essential building block for many electronic systems, such as analog-to-digital and digital-to-analog converters, and voltage regulators. Although state-of-the-art voltage references already demonstrated high performance over the standard temperature range (−40 °C to 125 °C), specific applications require an operating temperature far beyond this range. A relevant example is the electronic interface for quantum processors, for which voltage references that can operate down to cryogenic temperatures are needed. This thesis presents a CMOS-based voltage reference that can work over a wide temperature range from 4K to 300K. To achieve a low-drift, high-accuracy reference, it is designed based on the devices’ cryogenic behaviour to minimize the nonlinearities of the PTAT- (proportional to absolute temperature) and CTAT (complementary to absolute temperature) voltages and combine them to generate a stable output voltage. Dynamic compensation techniques are employed to reduce the effect of process variations and a switched-capacitor circuit is proposed to minimize the output ripple. The targeted specifications of this design are comparable with the state-of-the-art voltage references working at room temperature. To verify the performance at cryogenic temperatures, the design has been taped out in 40nm CMOS technology.

Noninvasive brain stimulation plays an essential role in diagnosing and treating diseases of the brain. This stimulation can affect disease-related changes in brain activation, inhibition, or connectivity. Ultrasound neuromodulation is a rapidly growing field of noninvasive brain stimulation. In a form of acoustic pressure waves, ultrasound can transmit mechanical forces to modulate neurons. The acoustic waves can be focused on a particular location with a spatial resolution that depends on the set frequency. Compared to other noninvasive brain stimulation methods, ultrasound neuromodulation is a safe and reversible method that can be used to accurately simulate neuronal circuits for the treatment of neurological diseases.

New medical ultrasound solutions, from ultrasound imaging to ultrasound neuromodulation and ultrasonic powering of medical implants, require a wearable form factor and low power consumption. In these applications, pulsers are the most power-hungry block since they deliver high voltages to the ultrasound transducers and transducers contain massive parasitic capacitance. The ultrasound transducer needs to be driven by a high voltage (HV) square wave so that it can generate desired pressure for ultrasound brain stimulation. Therefore, improving the power efficiency of the driver part is very important for the whole system.

The purpose of this thesis is to design an energy-efficient driver within a limited area. There are two energy-consuming parts in the driver circuit. One is the parasitic capacitance of HV transistors, and the other is the capacitance of the transducer. In order to achieve HV operations, the driver part is typically implemented with HV transistors which have massive parasitic capacitance and also consume large areas. To solve this problem, stacked 5 V CMOS transistors are implemented to replace HV transistors. As for the energy loss due to charging and discharging the ultrasound transducer, many energy-saving methods are introduced in the literature such as energy-replenishing technique, charge redistribution method, and multi-level pulse-shaping technique. The proposed design compared the advantages and disadvantages of these methods and made some improvements on the basis of these techniques.

This work presents a power-efficient high-voltage pulser to drive integrated lead zirconate titanate (PZT) ultrasound transducers for ultrasound medical applications. The proposed pulser employs charge redistribution technique by utilizing a storage capacitor to save part of the charges before discharging the transducer. Furthermore, HV transistors are replaced by stacked 5V CMOS transistors that allow delivering 10 V to the piezo transducer. The pulser is designed and simulated in 180nm CMOS technology with 10 V power supply and 15 MHz operating frequency. The simulation results demonstrate that the proposed circuit improves the power efficiency by 30.55$\%$ compared to the traditional class-D pulser.

This thesis investigates the performance limits and design challenges of two current-mode front-end concepts that target WiFi and mm-wave 5G applications, respectively. The first concept is a power amplifier (PA), which operates at 2.4GHz and is driven by a direct-digital RF modulator (DDRM). A design for the PA, which also includes a parallel-combining transformer (PCT), was proposed, taped and tested in the QUBiC Gen8 technology of NXP Semiconductors. The measured results yield a peak output power of 27dBm, power efficiency of 20%, and an adjacent channel power ratio (ACPR) of -33.05dBc. In the other concept, the DDRM drives a power mixer (PMIX) which up-converts the DDRM signal to mm-wave frequencies. For the PMIX-based front-end, multiple linearity enhancement techniques were proposed and evaluated using simulations. For both current-mode front-end concepts, an extensive analysis on the theoretical output power and power efficiency limit was performed. Although current-mode operation has a high linearity potential, fully reaching this potential turns out not to be trivial, due to various device non-idealities and imperfect impedance matching.

CMOS technology is one of the feasible solutions to meet the world’s growing demand for high data rates because it offers the prospect of SoC at a low cost. But, the PA forms the major bottleneck in making SoC because the PAs in high data rate wireless communication systems have the requirement of high-efficiency and good linearity even at backed-off power levels. Currently, PAs are mostly of classes A and B. Both of these are linear, but peak efficiencies are only 50% and 78% respectively. This thesis focuses on implementing Continuous Class F (CCF) PA for WiFi 802.11n over the bandwidth 2.1 - 2.7 GHz, which meets the requirement of high efficiency and good linearity even at backed-off power levels. The CCF PA overcomes Class F’s disadvantage of limited bandwidth as well as maintains peak efficiency of 90.7% over the entire bandwidth. The designed PA has four main blocks: the driver, inter-stage matching, output network, and output stage. The procedure to implement each of these blocks is explained extensively in chapters 3, 4, 5, and 6. The layout of the chip is carried out in TSMC 40 nm, and the chip size is 1.4 mm2. From simulations, the CCF PA has a maximum efficiency of 30 % and EVM of -25 dB at 3 dB back-off across the bandwidth 2.1 -2.7 GHz. The tapeout of the chip is planned in March 2021. Later, the chip can be tested and simulation results will be validated. To the best knowledge of the author, this is the first CCF chip at 2.4 GHz band.

An ASIC is presented for intra-vascular ultrasound imaging. Despite being connected via a single coaxial cable, it is able to pass arbitrary high voltage bipolar signals to the transducers for acoustic imaging. The thesis talks about the need to reduce the cable count to one and reviews the existing work in literature. It builds up on an existing single cable design and focuses on the transmit part to make it compatible to a large number of ultrasound imaging modes by allowing it to pass high frequency signals up to 20MHz and bipolar signal voltages up to ±25V . The chip is phantom powered and thus its power supply and signals are transmitted on the same cable. The transmit switch designed for this ASIC is powered by and controlled by an on-chip low voltage supply and circuitry. The prototype ASIC has been designed in TSMC 180nm HV BCD Gen2 technology. This single cable design has 16 elements for transmit and 64 elements in the receive mode and was evaluated using simulations.

This work focuses on addressing the fundamental limitation on the minimum cold start-up voltage that could be harvested from a thermoelectric element (TEG) for human-body wearable applications. For ultra-low DC voltages, the challenge translates to generating a timed-signal to amplify it up to a value that could be used to drive, say, a boost converter which can then start-up the entire energy module. Contemporary works have, thus, strived to accomplish this using a charge-pump-based or a transformer-based approach, which in turn imposes a limit on the minimum TEG voltage that can be harvested. The solution this work proposes is to decouple the Cold Start-up system from the TEG altogether and instead, use a piezoelectric element (PEH). This element being capable of producing a well-timed (AC) signal for free, based on human body vibrations, can potentially drive a boost converter. To this end, an integrated circuit (IC) is designed that can utilize the voltage from the PEH, amplifying it up to generate a well-controlled signal that could operate the boost converter. At the heart of this IC, is a self-reconfigurable charge pump that arranges its stages in different boosting ratios (without any complex logic or DSP) based on the input voltage, to allow for a maximum harvested power. The proposed self-reconfigurable architecture can potentially lead the charge pump to be load-variation-resistant. It achieves this by providing an almost constant voltage while increasing the power for higher load demands, at the same time maintaining a constant efficiency. Thus, the fully on-chip implementation in TSMC 0.18 um CMOS, can cold start-up the system from 25 mV of thermoelectric voltage to deliver an output voltage of 1 V at 56.5 % converter efficiency, consuming only 240.5 pW of dynamic power (simulation). The minimum Cold Start-up voltage and dynamic power were found to be 18 mV (ΔT = 0.1 K) and 231.6 pW respectively, to supply 1 V at 44 % converter efficiency. Moreover, in order to prove that the fundamental limitation on the Cold Start-up voltage has been addressed successfully, the IC was also simulated to check whether it can further be lowered. In this case, by providing a piezoelectric excitation voltage 73.3 mVRMS higher, the Cold Start-up voltage was found to be reduced to 15 mV to supply a constant 1 V at the load. It was also found that increasing the inductor value in this case, can also allow the energy module to support even lower Cold Start-up voltages.

The availability of photolithography machines is key in the semiconductor industry, as downtime generally incurs in immense economic loss. Time to market is also very important for suppliers of photolithography systems, such as ASML. Photolithography machines include numerous measurement systems that are frequently used for qualification and troubleshooting, most of which are required during normal operation. Due to increased costs and complexity, it would not be practical to include dedicated sensors for every machine performance parameter relevant for diagnosis, therefore many parameters regarded as non-critical are not monitored. However, in some cases the information about the behaviour of these parameters can be very valuable to find the root cause of a failure or defect promptly. In these cases, a Wireless Sensor Network (WSN) would allow for a temporary installation of a measurement system to monitor such parameters.

This work presents the design of a WSN for monitoring the dynamics performance of the WaferHandler (WH), which is one of the major subsystems of a photolithography machine. The scope of the project includes:

• The selection of a radio technology on which the network is based on.
• The hardware design of a wireless sensor node for measuring acceleration, based on commercial off-the-shelf (COTS) components.
• The identification and firmware implementation of key principles in which the communication protocol should be based on according to the requirements of the application.
• The estimation of the power consumption and lifetime of the network.
• The design and execution of experiments to assess the reliability of the proposed solution.

Among the requirements of the system, the size of the sensor nodes, the network synchronization accuracy, and the maximum power dissipation stand out as the main challenges. As the available space inside the WH is very scarce, the sensor nodes must have a compact form factor to fit in the locations where they are meant to be installed. The reliability of the system is greatly determined by its capacity to remain synchronized with relatively high accuracy during a measurement. This can be difficult to achieve in a harsh environment such as the inside of a machine, where interference and signal fading are expected to recurrently cause the loss of packets used for network synchronization.Packet re-transmission should not be abused to alleviate the problem, as the sensor nodes are required to operate in vacuum and overheating can become a problem.

This thesis describes the design of an ultra-low power temperature to digital converter. It is intended to monitor the excess heat produced during the wireless charging of implantable medical devices such as pacemakers. The TDC is designed to achieve an accuracy of ±0.1 °C (3 sigma) from 27 °C to 47 °C, and ±0.3 °C (3 sigma) from -40 °C to 85 °C after a 1-point trim. It also achieves a resolution of 0.01 °C at 10 Sa/s. The low power consumption (155 nW) is made possible by the implementation of a self-biasing BJT-core. Its low power consumption, accuracy, and resolution make it ideally suited for clinical temperature monitoring.