Low-Offset Magnetic Field Sensing using the Hall Effect

Abstract

CMOS Hall sensors consist of current-biased n-well plates that output magnetic-field dependent voltages. Offsets due to n-well inhomogeneity can then be suppressed by the spinning-current technique, which involves periodically rotating the direction of the biasing current and averaging the resulting output voltages. However, its effectiveness is limited by the JFET effect, which refers to the formation of a depletion region between the n-well and the p-type substrate due to the voltage drop across the n-well. This depletion region modulates the n-well resistance, and so is also a source of residual offset.

In this work, a CMOS Hall sensor is reported which employs voltage biasing and reads out the short-circuit Hall current. Compared to current biasing, this stabilizes the voltage drop across the n-well and significantly reduces the offset due to the JFET effect. Implemented in a standard 180nm CMOS process, the resulting sensor achieves a 3σ offset of 1.1μT with a noise floor of 60nT/√Hz. Compared to the state-of-the-art, these results represent a 3x reduction in offset, and a 5x improvement in resolution.