High-Dynamic-Range, Low-Power Digital-Input Direct-PWM Class-D Amplifier

Master Thesis (2022)
Authors

D.M. Lombardo (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Supervisors

Qinwen Fan (TU Delft - Microelectronics)

Faculty
Electrical Engineering, Mathematics and Computer Science, Electrical Engineering, Mathematics and Computer Science
Copyright
© 2022 Nick Lombardo
More Info
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Publication Year
2022
Language
English
Copyright
© 2022 Nick Lombardo
Graduation Date
31-10-2022
Awarding Institution
Delft University of Technology
Programme
Electrical Engineering
Faculty
Electrical Engineering, Mathematics and Computer Science, Electrical Engineering, Mathematics and Computer Science
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Abstract

Class-D amplifiers are quickly becoming the standard in many audio applications. Their highly efficient behavior and wide power range make these amplifiers more suitable than traditional Class A/AB audio amplifiers. Battery-powered devices are a particularly interesting sub-field due to their special demand for extended battery duration and higher efficiency. An output power lower than 2 W, along with good performances in terms of linearity and efficiency, is often required. Many stand-alone Class-D Amplifiers have analog inputs, making them susceptible to interference that negatively impacts their behavior. This problem can be mitigated by employing an insensitive input digital interface. Many standard solutions often require complex architectures, which limit these systems' reliability. This work proposes a digital-input class-D amplifier with a multi-level output stage that, together with a relatively low (480 kHz) switching frequency, reduces idle power consumption while achieving good linearity. Based on a 180 nm BCD technology, it can drive a 16-Ω load showing pre-layout simulated performances: -111.3 dB THD+N, 115.6 DR, 91.4 % peak efficiency, and 2.14 mW idle power consumption.

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