This paper presents a digital-input Class-D headphone amplifier that achieves low noise and low idle power simultaneously. Three key techniques enable this: a power-adaptive 3-level IDAC that scales power with signal level, an assistant IDAC that relaxes the first integrator's power consumption, and a dual-edge PWA modulator that minimizes loop filter swing. Fabricated in 0.18μm CMOS, it achieves 117.8dB DR, −102.2dB THD+N, 0.6mA idle current, and 92% peak efficiency when driving a 16Ω load.