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A -102.2dB THD+N, 92% Efficiency, 1.08mW Idle Power Digital-Input Class-D Amplifier with Power-Adaptive Techniques and Dual-Edge Pulse-Width Adjustment Modulator

Conference Paper (2026)
Author(s)

Miao Zhang (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Huajun Zhang (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Domenico Maria Lombardo (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Qinwen Fan (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Research Group
Electronic Components, Technology and Materials
DOI related publication
https://doi.org/10.1109/ISSCC49663.2026.11409038 Final published version
More Info
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Publication Year
2026
Language
English
Research Group
Electronic Components, Technology and Materials
Pages (from-to)
78-80
Publisher
IEEE
ISBN (electronic)
9798331589363
Event
2026 IEEE International Solid-State Circuits Conference, ISSCC 2026 (2026-02-15 - 2026-02-19), San Francisco, United States
Downloads counter
26
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Abstract

This paper presents a digital-input Class-D headphone amplifier that achieves low noise and low idle power simultaneously. Three key techniques enable this: a power-adaptive 3-level IDAC that scales power with signal level, an assistant IDAC that relaxes the first integrator's power consumption, and a dual-edge PWA modulator that minimizes loop filter swing. Fabricated in 0.18μm CMOS, it achieves 117.8dB DR, −102.2dB THD+N, 0.6mA idle current, and 92% peak efficiency when driving a 16Ω load.

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File under embargo until 07-09-2026