3.1 A 120.9dB DR, -111.2dB THD+N Digital-Input Capacitively-Coupled Chopper Class-D Audio Amplifier

Conference paper (2023)

Authors

H. Zhang Electronic Components, Technology and Materials - EEMCS , Electronic Instrumentation - EEMCS
Marco Berkhout Goodix Technologies
K.A.A. Makinwa Microelectronics
Q. Fan Microelectronics
Research Group
Electronic Components, Technology and Materials (EEMCS) (TU Delft)
Copyright: © 2023 H. Zhang, Marco Berkhout, K.A.A. Makinwa, Q. Fan
DOI
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https://doi.org/10.1109/ISSCC42615.2023.10067400
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Published Date

2023

Language

English

Reuse Rights

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronic Components, Technology and Materials

Abstract

Class-D amplifiers (CDAs) are widely used in audio applications where a high power efficiency is required. As most audio sources are digital nowadays, implementing digital-input CDAs results in higher levels of integration and lower cost. However, prior open-loop digital-input CDAs suffer from high jitter sensitivity and output-stage distortion. In [1], jitter sensitivity at small signal levels is mitigated using a buck-boost converter that adaptively lowers the supply at the expense of extra external components and reduced power efficiency. Prior closed-loop digital-input CDAs employing multi-bit current-steering [2] or resistive [3] DACs are less sensitive to jitter, but their DR is limited to about 115dB. DAC non-idealities and intermodulation distortion are also challenges, and prior works only achieved a peak textTHD+N of about -98textdB [2], [3]. This paper presents a digital-input CDA that achieves high DR by combining a low-noise capacitive DAC (CDAC) with dedicated techniques to mitigate DAC mismatch, lSI, and intermodulation distortion. A prototype implemented in a 0.18mum BCD process achieves 120.9dB DR and -111.2textdB peak textTHD+N. Furthermore, it can deliver 13W/23W at 10% THD into an 8Omega/4Omega load with a 90%/86% efficiency.