Neuromodulation is a promising treatment methodology for disorders of the brain. However, current clinical applications are primarily focused on a rudimentary form of neuromodulation, exclusively targeting individual regions in the brain. This has led to limitations in effective treatment options for patients suffering from neurological and neuropsychiatric diseases, with brain stimulation yielding a success rate of only 50% in 50% of patients after five years. In recent years, it has been strongly theorized that most brain disorders are emergent properties of pathological network connectivity rather than dysfunction of isolated brain regions. Targeting brain connectivity via neuromodulation is, therefore, a promising approach for improving treatment efficacy. This study aims at bridging this therapeutic gap by advancing treatment strategies towards network-based neuromodulation. To achieve this goal, a computational framework was designed and implemented that analyzes brain activity to identify biomarkers of abnormal connectivity networks. Furthermore, software pipelines for the construction of patient-specific,
virtual brain models were designed and implemented which enable analysis of simulated neural activity and connectivity networks, and enable in silico neuromodulation. The framework is tested and validated using an EEG dataset consisting of neural-activity recordings belonging to patients diagnosed with neuropathic pain and a separate healthy control group. Our computational framework shows high ability in identifying disease-specific abnormalities in network connectivity and in constructing pathological network hubs, with accuracies up to 98.6% in explaining neuropathic pain. Patient-specific,
brain-model construction is also able to accurately represent empirical patterns of connectivity in simulation. Furthermore, the simulated neuromodulation with personalized virtual brains demonstrates the ability to accurately model dynamic modulation of brain connectivity networks. These findings illustrate the effectiveness of our overall framework and highlight the potential for integration into clinical decision-making and closed-loop implantable neuromodulation systems, enabling more effective treatment of brain disorders.

With the prosperity of the Internet of Things (IoT) and artificial intelligence (AI), more and more edge devices have been deployed to enable intelligent applications. However, due to the limited energy budget and computation resources, it is challenging to deploy deep neural networks on edge devices directly. The energy consumption of the memory transfer between the processor and memory is a significant part of the total energy consumption, which is the bottleneck of traditional von Neumann architecture. Computation in memory (CIM) is a promising architecture that can significantly reduce this energy consumption by minimizing the data movement between the processor and memory. By utilizing the novel non-volatile memory (NVM) technology, the computation can be performed in the memory in analog domain, which can reduce the energy consumption and latency of the computation. However, the existing periphery of CIM architecture, which is responsible for converting the result of the computation in memory to the digital domain, is not energy-efficient and has a large area overhead. In this thesis, we propose a novel AI-based periphery for CIM architecture to address these issues. The proposed periphery is based on the neural network, which can be trained to convert the crossbar output to the digital domain with high accuracy. Multiple inputs, up to four crossbar columns with different significant levels, can be processed simultaneously and output the shift-and-add result in the digital domain in one shot, without the need for multiplexers or post-processing circuits. Moreover, a new coding scheme called natural Palindromic Coding (NPC), is proposed to encode the output of the neural network, which aims to mitigate the spectral bias of the neural network, where high-frequency components, like the least significant bit (LSB), are underrepresented. Benchmarking results show that the proposed AI-based periphery, with 4 parallel 4-bit inputs and 8-bit output, can achieve 81.16% accuracy or 99.5% accuracy with 1 unit step tolerance. Under the MNIST dataset, the proposed NPC can achieve an accuracy of 96.80%, compared with 97.07% of software inference. In addition, the proposed periphery can achieve 31.77× energy saving and 9× area saving compared with the state-of-the-art neural-network-based periphery, or up to 1.65× energy saving and 2.70× area saving compared with the state-of-the-art SAR-ADC-based periphery.

Neuromorphic systems offer a promising solution to the computational challenges of intra-cortical Brain-Computer Interfaces (iBCIs), leveraging the event-driven nature of biological neural networks for enhanced power efficiency and data scalability. The exponential growth in neural data rates due to advancements in high-density neural recording creates significant hurdles in data transmission and processing. This paper introduces a novel neuromorphic compression architecture that combines delta-modulated level crossing events with Spiking Neural Networks (SNNs) trained through a two-stage process with grouped inputs. The proposed system achieves a compression ratio exceeding 94× and a peak Signal-to-Noise and Distortion Ratio (SNDR ) of 22 dB compared to the signal without Local Field Potentials. This substantial improvement over existing methods drastically reduces data throughput making it ideal for implantable devices where resource constraints are critical. Validated on hippocampal and cerebellar datasets, our approach significantly outperforms state-of-the-art techniques in terms of computational and compression efficiency, SNDR, and memory usage—requiring just 384 bits per channel to store necessary data for processing and 18.07K Multiply and Accumulate operations (MACs) per spike. These findings underscore the potential of neuromorphic SNNs as a transformative technology for future iBCIs, advancing neural prosthetics and brain-machine interfaces.

Ultra-low power Edge AI hardware is in increasing demand due to the battery-limited energy budget of typical Edge devices such as smartphones, wearables, and IoT sensor systems. For this purpose, this Thesis introduces an ultra-low power event-driven SRAM-based Compute In-Memory (CIM) accelerator optimized for inference of Binary Spiking Neural Networks (B-SNNs). In this Thesis, a custom-designed 3nm SRAM cell is developed, with up to four read ports to improve inference performance and one transposable read/write port for efficient on-chip learning functionality. The event-based nature of SNNs is exploited to minimize the computation and memory cost. The design benefits from technology scaling of fully digital design by synthesizing the accelerator in the imec 3nm FinFET technology node. The proposed accelerator's performance is evaluated by running MNIST inference at 97.6% accuracy, achieving an impressive throughput of 44M inferences/s at 607 pJ/inference (3.2 fJ per synaptic operation) while running at 29 mW. The results demonstrate that the proposed accelerator provides an energy-efficient and high-performance solution for inference of Binary SNNs, opening up new possibilities for Edge AI applications.

The ever-increasing energy demands of traditional computing platforms (CPU, GPU) for large-scale deployment of Artificial Intelligence (AI) has spawned an exploration for better alternatives to existing von-Neumann compute architectures. Computation In-Memory (CIM) using emerging memory technologies such as Resistive Random Access Memory (RRAM) provide an energy-efficient and scalable alternative for Deep Neural Networks (DNN) applications. However, the benefits of CIM frameworks come at the cost of low DNN accuracy due to non-idealities in RRAM devices. In this thesis we address the conductance variation non-ideality in RRAM devices at an architectural level. We present two mapping schemes to improve the accuracy of CIM-based DNNs in the presence of RRAM conductance variation. Experimentation conducted with five datasets show that all proposed schemes provide up to 5.4x accuracy improvement over state-of-the-art implementations while inducing a 1.5% area cost and up to 10% energy overhead. Based on accuracy-energy trade-off, the thesis concludes the proposed Complementary Conductance Matrix (CCM) is the best candidate to improve inference accuracy of neural networks on CIM hardware using RRAM. It reports an accuracy improvement up to 5x with 1.52% area overhead and 9% energy overhead.

As of 2021, the world economic forum deems cyber-security failures as one of the most potent threats to the world. According to a McAfee report, the cost of cybercrimes in 2020 reached nearly 1 trillion US dollars, which was around 50 percent more than what it was in 2018. Exacerbating the already mammoth financial implication of such a failure is the ever-growing diversity in cyber attacks. Side-channel analysis is one such attack type wherein the information leaked via the implementation of a cryptographic algorithm is leveraged to obtain secret data, rather than any weaknesses in the cryptographic algorithm itself. This leaked information, amongst others, can be in terms of power, EM radiation, or the time taken to perform a cryptographic operation. Countermeasures against such side-channel attacks aim at reducing the amount of information leaked via the side channels or reducing the correlation between the secret operations and the information leaked. Manufacturing the chip is often a prerequisite for evaluating the efficacy of such countermeasures, which is a costly and time-consuming process. Thus, the security evaluation of a design has a substantial impact on the design cost and the time to market. In case the design does not meet minimum security requirements, it has to be redesigned and manufactured, increasing not only costs but also the design time considerably. Hence, there is a need for pre-silicon leakage assessment tools that can provide designers a sense of certainty about the security aspects of their design. However, the existing pre-silicon leakage assessment tools are either deemed unreliable or too slow to be used to perform power leakage assessment, which is the problem this thesis aims to ameliorate. This thesis explores the use of generative adversarial networks (GANs) for generating synthetic power traces. Generative deep learning has been used in various domains like computer vision, audio, and even for medical data like ECG. GANs have been introduced in the context of side-channel attacks to enlarge the size of the profiling dataset for carrying out profiled side-channel attacks. In this work, we propose a robust methodology to condition and train GANs to generate power traces that can be used to carry out leakage assessment. This methodology can even be extended to support the design space exploration of countermeasures by providing reliable leakage assessment at design time. The generated power traces are not only indistinguishable but also as attackable as the real traces. The conditioning technique helps the GAN to generalize to various scenarios and the proposed framework provides a speed-up of around 140 times over traditional CAD methods to simulate power traces while maintaining their structure and accuracy.

Some server hosters facilitate cyber crime either intentionally (so called “bulletproof hosters”) or unintentionally (“bad hosters”). When dealing with uncooperative hosters during forensic investigations, it may sometimes be necessary to collect data or information on the servers without help from the owner of the server. Data within the RAM might prove insightful in, for example, determining active processes or reveal crypto graphically interesting information like encryption keys. The thesis explains key concepts within memory organization and the PCIe standard.Afterwards, it discusses several techniques for RAM acquisition and categorizes and evaluates them using a model-based approach. The thesis then dives deeper into DMA-based memory acquisition using PCIe and proposes several improvements to current DMA attacks in order to create a better memory acquisition technique. A novel memory acquisition technique is created by hot-plugging aPCIe device and skipping over the regular enumeration procedure. This techniqueal lows the memory acquisition to be executed without a reboot and provides a stealth approach to accessing the memory.  

The adoption of Microprocessors is increasingly diversifying to several embedded and mo- bile devices. Growingly they can also be found in Smart Cards, RFID tags, SIM cards, Pay TVs, identity cards and passports. These devices store, processes and transact sensitive information like social security numbers and credit card numbers. Ensuring security of such systems is of paramount importance. Attackers use Fault injection as one of the tech- niques to induce faults into the processor in order to gain access to the sensitive information to abuse it. Vulnerability Analysis of the processors can help chip designers to counteract some of these risks. This analysis can be achieved by investigating the resulting fault space upon exhaustive simulation of fault injection attacks. Therefore, efficient tools and frame- works are needed to provide such security verification, where critical vulnerabilities can be discover and mitigated at design-time. Multiple tools and frameworks for simulation based fault injection of hardware designs are available in literature, each with their own shortcomings. Two main strategies have been proposed in literature, one based on tool manipulation while other based on code modifica- tion. Applying tool manipulation, a designer can automate the process to inject faults in the system and obtain simulation results in a fast manner. However, this approach is limited by the features provided by the tool, which makes difficult to explore many different fault models. Additionally, in most cases, results require manual inspection to be interpreted. The latter approach, which is code modification, can inserts agents to cause the faults (i.e., saboteurs) or vary the existing design (i.e., mutants). It allows designers to achieve a high degree of control in terms of the type of fault and the injection method. However, current so- lutions are limited to a specific language, design or scenario. Hence, the literature presents many different strategies and tools to apply faults to investigate hardware behavior, but still the interpretation of vulnerabilities related to processors are not considered in such tools. Moreover, a complete automated framework capable to get a design and process it to report vulnerabilities and behavior issues related to security is still needed. This thesis proposes a framework that provides a complete toolset able to evaluate vulner- abilities of processors in hardware description language. Its main steps comprises design instrumentation, simulation based fault injection and automatic fault classification. RISC-V is chosen as the target architecture due to its open source nature and its increasing adoption by academia and industry. Code profiling was carried out on the frameworks to identify bot- tlenecks to performance. The results were used to optimise execution time of simulations using the framework. Performing Fault injection campaigns requires running simulations in the order of 100k, which requires systems with high computing power to complete them in reasonable time. Therefore, multiprocessor support was implemented in simulation frame- work, which could be enabled or disabled during the injection campaign. The framework was used to perform fault injection campaigns on PicoRV32 and DarkRISCV processors. A comparison between the processors is made based on their major failure signatures. Anal- ysis of finding design constructs in the processors which cause the major failure signatures was carried out. The results from this vulnerability analysis are used to propose software and hardware countermeasures to make the design more robust against fault injection.

Hardware implementations of encryption schemes are unprotected against side-channel analysis techniques. Physical realizations of secure algorithms leak side-channel information through power, noise, time, sound and electromagnetic radiation. Data-dependent correlations with this leakage are exploited to obtain secret information. Power analysis techniques are powerful, undetectable and non-intrusive attacks that allow an adversary to extracts the secret key of the encryption scheme. These techniques rely on analyzing the power consumed by these physical realizations using leakage models and statistical techniques.

Implementing a countermeasure against power analysis attacks require a thorough understanding of the attack, encryption algorithm and it's implementation on hardware and software. Conventional countermeasures for AES against power analysis techniques minimize the side-channel information by implementing masking and hiding strategies at different abstraction levels. This thesis investigates a new class of countermeasures known as "breaking" through the implementation of the Substitution Box transformation using a neural network (S-Net). The inherent properties associated with the neural network architecture is expected to remove the correlation between the power consumed and the secret key used for encryption by breaking the linear power characteristics assumed by the leakage model.

The proposed approach was implemented in software and an attack framework is used to run side-channel attacks and quantify information leakage. The effectiveness of the implemented countermeasure is measured by checking and quantifying it's security against Differential and Correlation Power Analysis, Template and Deep Learning based techniques. The results indicate that the implementation is secure against these attacks.

Forensic science is the cornerstone of the modern justice system, as it allows us to analyze evidence in order to discover the truth behind a crime scene. As mobile phones became more important to our daily lives they've taken up a bigger part in forensic research as well. These devices contain digital traces telling us the story of our lives. Digital forensic research traditionally focused on recovering data, in particular data from broken or undocumented systems. While security was not the primary concern of most manufacturers, this has changed in recent times. Cryptography has become a major roadblock in forensic science, which has shifted the focus from recovery towards exploitation. Traditionally Digital forensic research focused on physical acquisition. While often tools supported logical extraction, this would leave many deleted traces inside of the memory chip intact. Instead methods such as Flasher tools, JTAG-based acquisition, In-System Programming and Chip-off were often used to make images of the physical contents of the memory chip. This would then be analyzed by data-analysts in order to extract evidence from the images. On many modern devices cryptography has ensured that these methods are no longer effective. Software exploitation techniques such as DirtyCow have proven to become much more important in digital forensic science, but more methods should be developed. JTAG is of particular interest in this regard. It is a testing system that was previously left unsecured and providing attackers with an easy way in. More recently manufacturers have started using novel ways of protecting JTAG from malicious use, but very little research exists testing these new security measures. This is a recipe for vulnerabilities. This thesis focuses on attacking Secure JTAG; Samsung's authentication module for ARM CoreSight. Several potential attacks have been highlighted that are potentially applicable to Secure JTAG. A novel model has been developed that allows an attacker to evaluate the complexity of their attacks. While models such as CVSS and DREAD exist, these focus on threat analysis rather than offensive research. Using this model two attacks were chosen: One focusing on reversing the internal JTAG boundary scan chains and the other attempting to force authentication through fault injection. In order to reverse the JTAG boundary scan chains a new set of tools had to be developed. Existing tools were often incapable of communicating with the internal scan chains or did not provide enough freedom to enable research. After their development these new tools were able to confirm that the internal scan chains were secured. The internal boundary scan chains will not be a viable attack vector until the authentication mechanism is circumvented. The second attack focused on a potential fault injection vulnerability in the Secure JTAG authentication scheme. Because Secure JTAG is a purely hardware component it provided a unique challenge. Where normally firmware is analyzed to prove the existence of a vulnerability, Secure JTAG has no such firmware available. This makes discerning between failure because the device is not vulnerable and failure because of chance nearly impossible. To increase confidence in the attack and decrease attack space this project focused on Electromagnetic Side-channel Analysis. By locating the signals produced by Secure JTAG authentication it is possible to greatly reduce the attack space, thereby increasing confidence in the attack. In the end correlating signals were located near the high-power processor of the chip, albeit not the hashing engine itself. This lowered the attack space enough for an eventual fault injection attack.

This report discusses one part of a project consisting of three parts. The goal of the project is to design a battery less sensor powered by RF energy fields present in an office environment. The sensor is able to measure the temperature and is able to communicate wirelessly using a low power communication protocol.In this report the energy conversion and storage of the system will be discussed. A high-frequency signal coming from an antenna must be converted to an output signal which is functional for the communication module. Therefore a steady 3.3 V DC output needed to be created with a rectifier circuit. In order to achieve maximum power transfer to the load, a matching circuit with the RF energy harvesting antenna needed to be designed. The main challenges were to achieve a high enough input voltage to reach the threshold voltage of the diodes of the rectifier and to rectify the AC input as efficient as possible. To tackle these challenges a design with a Greinacher rectifier with low-threshold Schottky diodes and a DC/DC booster is presented.