This thesis presents an ultra-low power wakeup timer locked to an RC time constant that can meet the stringent power requirements of the nodes for Internet-of-Things (IoT) applications. The wakeup timer, fabricated in a 40-nm CMOS process, employs a bang-bang digital-intensive frequency-locked loop (DFLL). A self-biased ΣΔ digitally controlled oscillator (DCO) is locked to an RC time constant via a chopped dynamic comparator and a digital loop filter, enabling an operation down to 0.65 V and a small area of 0.07 mm2. The digital-intensive design consumes 181 nW with an output frequency of 417 kHz. Thus, it achieves the best power efficiency (0.43 pJ/Cycle) at the lowest supply voltage (0.7 V nominal) over the state-of-the-art for ultra-low-power timers, while keeping on-par long-term stability (Allan deviation floor below 10 ppm) and temperature stability (106 ppm/°C).

While there are many technologies and electronic systems used to detect the human vital signs by monitoring the heart beat rate & respiration rate, all these systems rely on physical contact with the human body. Furthermore, each measuring system can only be used for a single person thus increasing the cost and complexity of integrated systems to monitor many persons simultaneously. For remote vital signs and occupancy detection in many smart home/building applications, radar sensors are a preferred option over cameras, due to privacy preservation and robustness to ambient light conditions. These radars not only need to provide precise range and vital signs information over meters distance, but also preferably can operate on a battery up to a few months or even years, for cost and practical reasons (like smoke detectors). This project aims at sensing the vital signs and estimating the heart beat rate and respiration rate with no physical contact with the person and single system can be employed to monitor the parameters for multiple persons powered by battery that can last for months. Thanks to radar technology and signal processing algorithms that enable to implement such a hardware efficiently. In this work [1], the fast settling frequency locked loop(FLL) and Receiver front-end are designed and evaluated for the radar transceiver following the various design trade-offs obtained by comprehensive system simulations to derive the specifications for the related circuit design blocks in 40 nm CMOS technology to detect the vital signs of multiple persons as close as 20 cm till the distance of 15m from the radar system by consuming a total average power of 680µW and satisfying the spectral regulations in US, Europe, Korea, China and Japan.