Intracortical brain computer interfaces hold the potential to revolutionize neurotherapeutics, but they must overcome technological challenges such as the high data rates generated by high-channel-count neural sensors and the stringent power and volume constraints of implantable devices. In addition, the brain-wide coverage needed for a deeper understanding of brain processes challenges the synchronization between distributed neural sensors and the central neural hub. To address these challenges, we present a deterministic-latency and power-efficient serializer–deserializer (SerDes) telemetry network that effectively mitigates the synchronization issue under strict power and volume constraints. The serializer on the sensor side employs event-based sampling and a packet-based address-event representation transmission protocol, achieving a low power consumption of only 127 µW and a low latency variation <10 µs. A crystal-free clock source is employed on the sensor side to minimize power consumption, with serialized data encoded using Manchester coding scheme. The deserializer on the hub handles the bit period uncertainty by counting and extracting the bit period of received data with a clock only ∼2.2× faster than the serializer clock. The proposed counting-based Manchester decoder achieves a wide frequency coverage up to 204 000 ppm of frequency variation. The deserializer achieves a measured Manchester decoding bit error rate (BER <10−6), with a total estimated power consumption below 415 µW. The SerDes performance has been validated with in vivo pre-recorded data, demonstrating a compression ratio greater than 7, while preserving a high signal fidelity with an average RMSE <6 µVRMS.

This paper presents a wakeup timer in 40-nm CMOS for Internet-of-Things (IoT) applications based on a bang-bang Digital-intensive Frequency-Locked Loop (DFLL). A self-biased Σ Δ Digitally Controlled Oscillator (DCO) is locked to an RC time constant via a feedback loop consisting of a single-bit chopped comparator and a digital loop filter, thus maximizing the use of digital circuits while keeping only the RC network and the comparator as the sole analog blocks. Analysis and behavior level simulations of the DFLL have been carried out to guide the optimization of the long-term stability and frequency accuracy of the timer. High frequency accuracy and a 10× enhancement of long-term stability is achieved by the adoption of chopping to reduce the effect of comparator offset and 1/f noise and by the use of Σ Δ modulation to improve the DCO resolution. Such highly digitized architecture fully exploits the advantages of advanced CMOS processes, thus enabling operation down to 0.7 V and a small area (0.07 mm2). The proposed timer achieves the excellent energy efficiency (0.57 pJ/cycle at 417 kHz at 0.8-V supply) over prior art while keeping excellent on-par long-term stability (Allan deviation floor < 20 ppm) and temperature stability (33 ppm°Cat 0.8-V supply).

For remote vital signs and occupancy detection in many smart home/building applications, radar sensors are a preferred option over cameras, due to privacy preservation and robustness to ambient light conditions. These radars not only need to provide precise range and vital signs information over meters distance, but also preferably can operate on a battery up to a few months or even years, for cost and practical reasons (like smoke detectors). State-of-the-art remote vital-sign sensors typically use an impulse-radio UWB (IR-UWB) radar [1,2] because it provides a range resolution <20 cm. However, their power consumption is typically in the order of 100's of mW, preventing long-term maintenance-free battery-powered operations. Although mains power can be used to supply such radars, this is not always available, depending on the location and the building type, and the installation cost (e.g., power routing) is significantly higher than for battery-powered ones. In this work, a burst-chirp radar with an energy-efficient chirp generation is proposed, leading to a record-low power consumption of 680 μW.

A 40-nm CMOS wakeup timer employing a bang-bang digital-intensive frequency-locked loop for Internet-of-Things applications is presented. A self-biased ΣΔ digitally controlled oscillator (DCO) is locked to an RC time constant via a single-bit chopped comparator and a digital loop filter. Such highly digitized architecture fully exploits the advantages of advanced CMOS processes, thus enabling operation down to 0.7 V and a small area (0.07 mm 2 ). Most circuitry operates at 32× lower frequency than the DCO in order to reduce the total power consumption down to 181 nW. High frequency accuracy and a 10× enhancement of long-term stability is achieved by the adoption of chopping to reduce the effect of comparator offset and 1/f noise and by the use of ΣΔ modulation to improve the DCO resolution. The proposed timer achieves the best energy efficiency (0.43 pJ/cycle at 417 kHz) over prior art while keeping excellent on-par long-term stability (Allan deviation floor <;20 ppm) and temperature stability (106 ppm/°C).

This paper presents a 1.8-2.7 GHz low-power ring-oscillator-based fractional-N injection-locked digital PLL (IL-DPLL) in 40-nm CMOS for Internet-of-Things clock generation. A two-path injection technique is proposed to improve the in-band phase noise and the integrated jitter of the implemented PLL by 6 dB and 1.8×, respectively. Furthermore, a digital foreground calibration is introduced to effectively reduce reference spurs in a short calibration time of 2 μs. In the worst-case channel, the proposed DPLL using a 64 MHz reference input shows a 1.6 ps integrated jitter, -43.6 dBc reference spur, -45.8 dBc fractional spur and 1 kHz frequency resolution while consuming 1.33 mW power.