Neuromorphic systems offer a promising solution to the computational challenges of intra-cortical Brain-Computer Interfaces (iBCIs), leveraging the event-driven nature of biological neural networks for enhanced power efficiency and data scalability. The exponential growth in neural data rates due to advancements in high-density neural recording creates significant hurdles in data transmission and processing. This paper introduces a novel neuromorphic compression architecture that combines delta-modulated level crossing events with Spiking Neural Networks (SNNs) trained through a two-stage process with grouped inputs. The proposed system achieves a compression ratio exceeding 94× and a peak Signal-to-Noise and Distortion Ratio (SNDR ) of 22 dB compared to the signal without Local Field Potentials. This substantial improvement over existing methods drastically reduces data throughput making it ideal for implantable devices where resource constraints are critical. Validated on hippocampal and cerebellar datasets, our approach significantly outperforms state-of-the-art techniques in terms of computational and compression efficiency, SNDR, and memory usage—requiring just 384 bits per channel to store necessary data for processing and 18.07K Multiply and Accumulate operations (MACs) per spike. These findings underscore the potential of neuromorphic SNNs as a transformative technology for future iBCIs, advancing neural prosthetics and brain-machine interfaces.

This thesis presents an ultra-low power wakeup timer locked to an RC time constant that can meet the stringent power requirements of the nodes for Internet-of-Things (IoT) applications. The wakeup timer, fabricated in a 40-nm CMOS process, employs a bang-bang digital-intensive frequency-locked loop (DFLL). A self-biased ΣΔ digitally controlled oscillator (DCO) is locked to an RC time constant via a chopped dynamic comparator and a digital loop filter, enabling an operation down to 0.65 V and a small area of 0.07 mm2. The digital-intensive design consumes 181 nW with an output frequency of 417 kHz. Thus, it achieves the best power efficiency (0.43 pJ/Cycle) at the lowest supply voltage (0.7 V nominal) over the state-of-the-art for ultra-low-power timers, while keeping on-par long-term stability (Allan deviation floor below 10 ppm) and temperature stability (106 ppm/°C).