A Digital-Intensive Wakeup Timer based on an RC Frequency-Locked Loop for Internet-of-Things Applications

Master thesis (2017)

Authors

Z. Zhou Electrical Engineering, Mathematics and Computer Science

Contributors

F. Sebastiano (supervisor 1)
Ming Ding (supervisor 1)
Yao-Hong Liu (supervisor 2)
Faculty
Electrical Engineering, Mathematics and Computer Science
Copyright: © 2017 Zhihao Zhou
IoT Oscillator Wakeup timer FLL
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Published Date

27-11-2017

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Abstract

This thesis presents an ultra-low power wakeup timer locked to an RC time constant that can meet the stringent power requirements of the nodes for Internet-of-Things (IoT) applications. The wakeup timer, fabricated in a 40-nm CMOS process, employs a bang-bang digital-intensive frequency-locked loop (DFLL). A self-biased ΣΔ digitally controlled oscillator (DCO) is locked to an RC time constant via a chopped dynamic comparator and a digital loop filter, enabling an operation down to 0.65 V and a small area of 0.07 mm2. The digital-intensive design consumes 181 nW with an output frequency of 417 kHz. Thus, it achieves the best power efficiency (0.43 pJ/Cycle) at the lowest supply voltage (0.7 V nominal) over the state-of-the-art for ultra-low-power timers, while keeping on-par long-term stability (Allan deviation floor below 10 ppm) and temperature stability (106 ppm/°C).