As digital systems continue to scale toward advanced technology nodes, hardware reliability has become increasingly critical, especially in large-scale computing environments where even rare failures can lead to Silent Data Corruption (SDC). Unlike detected hardware errors, SDCs may propagate unnoticed through the hardware and software stack, causing incorrect results, data corruption, and costly debugging procedures. Conventional manufacturing test strategies, such as stuck-at, transition-delay, and path-delay fault models, are often insufficient to capture the complex behavior of emerging physical defects and process-induced variations.
This thesis investigates the application of Device-Aware Test (DAT) to logic circuits as a methodology to reduce escapes and increase the fault coverage by linking physical defect characteristics – i.e., technology parameters – to their electrical impact – i.e., electrical parameters. The work focuses initially on interconnect-level defects affecting vias, and secondly on transistor-level pinhole defects in low-nanometer technologies. In both cases, the extracted electrical impact of the defects is subsequently propagated to circuit level through fault modeling, where defect-induced effects are evaluated in terms of functional degradation and propagation
delay. These fault models then guide test development by identifying the circuit conditions, gates and paths under which the defect-induced effects are most likely to become observable. For via-related defects, the complete flow is also validated by comparing conventional timing-driven path-delay testing with a Device-Aware strategy that additionally targets physically vulnerable, via-rich paths. The results show that defects escaping the conventional test can be detected when physical vulnerability is explicitly included in ATPG target selection.
Overall, this thesis demonstrates the potential of DAT to improve the detection of hardware defects and support more reliable operation of advanced logic circuits. ... Read more

The efficiency of accelerating Deep Neural Network (DNN) workloads on dedicated hardware accelerators is heavily influenced by the mapping, which specifies how a workload is distributed across the accelerator's caches and parallelized across its compute elements. These choices create a combinatorially large space of possible mappings, many of which do not satisfy the hardware's resource constraints, such as the memory capacity of different buffers. Most existing automated mappers restrict this search space to "perfect factorization", considering only mappings where tiling factors and spatial unrollings perfectly divide the workload dimensions, and excluding mappings that could achieve much higher resource utilization. While some frameworks relax this constraint to allow imperfect factorization, doing so significantly expands the search space. Existing search strategies struggle to navigate this expanded, sparsely feasible space, leaving many of the highest-performing mappings out of reach.

This work introduces IMPACT, a mapping framework designed to search the space of fully imperfectly factorized mappings. IMPACT integrates a constraint-aware repair operator into a genetic algorithm. Instead of generating infeasible mappings during genetic crossover and mutation, the repair operator uses a Metropolis-Hastings walk combined with simulated annealing to discover valid mappings near invalid ones. Evaluated on the widely used Eyeriss hardware accelerator for the DeepBench benchmark, IMPACT outperforms other SoTA mappers and a constraint-unaware version of the genetic algorithm, achieving a mean improvement of 25\% for energy consumption over Timeloop. On a more complex and constrained compute-in-memory architecture, IMPACT's advantage grows, reducing the energy-delay product by 90\%, latency by 74\%, and energy by 30\% and achieving results that rival hand-crafted mappings designed by experts.

This framework demonstrates the potential of constraint-aware search to automate the generation of high-quality mappings for both more flexible accelerators and complex, specialized ones. The findings highlight the critical importance of constraint awareness for mapping space exploration frameworks and encourage integrating constraint-aware heuristic search into compiler workflows.
... Read more

Ferroelectric Field-Effect Transistors (FeFETs) are incredibly promising for the next wave
of computing among emerging NVMs because of their ability to perform as both logic and
memory device and low operation power, especially in areas like computation-in-memory and
neuromorphic applications. However, a hurdle to their adoption has been the lack of an open-
source, physics-based simulation model that is both accurate and SPICE-compatible. Existing
models often fall short by not accouting for the polycrystalline physics of the ferroelectric material,
and they don’t always account for crucial effects like leakage currents. This thesis introduces an
open-source SPICE-compatible FeFET model built on the Nucleation-Limited Switching (NLS)
framework, which is designed to accurately capture the time-dependent nature of the device’s
polarization. This model is validated by comparing its output against actual experimental data
from fabricated FeFETs and FeCAPs. A key part of this work was integrating non-ideal effects
like temperature changes and device-to-device variations, making the model more robust. The
model’s functionality is tested by simulating core FeFET operations including non-volatile
writes and non-destructive reads, and demonstrated its application within a multiply-and-
accumulate circuit which is used in computation-in-memory applications. Ultimately, this
thesis provides a reliable simulation model that includes a physics-based implementation of
hysteresis and leakage current effects that can be used to design and simulate circuits with
computation-in-memory applications. ... Read more

Modern Artificial Intelligence (AI) applications, such as Deep Neural Networks (DNNs), require substantial amounts of data in order to carry out the classification or recognition task, which must be retrieved from the memory, supplied to the processor, and finally the results stored back in the memory. In Von-Neumann architectures, this data movement incurs significant performance costs, leaving the CPU with many idle cycles while waiting for data to arrive. One way of addressing this issue is by investigating alternative computing paradigms, such as Computation in Memory (CIM). In CIM architectures, the processor and the memory are integrated into one physical location. As such, computations are performed in the memory core directly, without the need to be transferred to a central processor. A promising technology to efficiently implement CIM crossbar arrays is the emerging Ferroelectric Field Effect Transistor (FeFET), in which data can be stored in a non-volatile manner in the polarization state of a ferroelectric layer.

In existing literature, CIM crossbar arrays are optimized for the inference task, but do not perform the learning task locally. This means the neural network is trained externally, for example using cloud computing. Only once the training is finished, the weights are written to the physical crossbar array. For medical applications, such as ECG classification, sending sensitive medical data off to the cloud for training leads to privacy concerns. A solution to this problem is On-chip learning: training the network locally in the crossbar itself.

This thesis focuses on integrating the FeFET technology in a CIM architecture to design a crossbar array that supports On-Chip learning for Convolutional Neural Networks. The accelerator overcomes the memory-wall inherent to Von Neumann machines by embracing the CIM framework and uses FeFET devices to overcome the scaling walls associated with CMOS technology. The result is a novel accelerator which leverages the parallelism of Analog Crossbars to optimize the inference task and forward propagation, while leveraging the accuracy of Digital Crossbars to optimize the back propagation task. ... Read more

Event-driven neural network accelerators achieve superior energy efficiency by processing only meaningful data events, yet existing design space exploration tools lack support for their asynchronous execution characteristics. This thesis introduces AeDAM (Event-Driven Architecture Mapping), a specialized framework for systematic exploration of event-driven accelerator architectures.

AeDAM transforms traditional synchronous mapping methodologies into event-driven configurations through intelligent Loop Order Memory Access scheduling and specialized analytical cost models for asynchronous dataflows, targeting energy-delay product optimization.
Experimental validation using the SENECA neuromorphic architecture demonstrates substantial improvements: 2.5× faster exploration times, 13-52% latency reductions across VGGNet layers, and 12× energy-delay product improvements. Optimal configurations feature 512KB SRAM capacity and multi-dimensional processing element arrays.

AeDAM establishes a foundation for systematic exploration of energy-efficient event driven computing systems targeting edge applications. ... Read more

Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising technology, but its mass production is challenged by manufacturing defects, particularly those introduced during the Magnetic Tunnel Junction (MTJ) fabrication. Traditional testing methods fall short due to unique defect types. This dissertation addresses this by developing effective test and diagnosis methodologies, following a three-step approach: defect modeling, fault modeling, and test generation. It classifies defects into conventional ones (modeled as linear resistors) and unique MTJ defects (modeled using a Device-Aware Test (DAT) method, which this work extends to the Back-hopping (BH) defect). The thesis incorporates MTJ specific behaviors like stochasticity into fault modeling and designs efficient March tests and Design-for-Test (DfT) solutions to ensure high fault coverage. Furthermore, it introduces Device-Aware Diagnosis (DA-Diagnosis) for cost-effective identification of unique defects, demonstrating the practical feasibility of the proposed methodologies through implementation in an STT-MRAM array. ... Read more

This dissertation, conducted within the discipline of Electronic Science and Technology (specialization in Microelectronics and Solid-State Electronics), focuses on Resistive Random Access Memory (RRAM), an emerging non-volatile memory technology known for its high density and zero static power consumption. RRAM enables fast write and read operations in the nanosecond range and supports Computation-in-Memory (CIM), making it a strong candidate to replace Flash or even Dynamic Random Access Memory (DRAM). Recognizing its potential, both academic institutions and industry leaders have been actively developing RRAM prototypes, with some already reaching the commercial market. To ensure reliability, high-quality testing is essential for guaranteeing product quality.

This dissertation mainly focuses on developing effective test methodologies and robust designs for RRAMs. We begin by examining the RRAM manufacturing process and identifying potential physical defects at each stage through a comprehensive literature review and silicon measurements. To facilitate in-depth analysis, we develop a complete and systematic RRAM simulation platform, integrating a MATLAB-based simulation controller and fault analysis scripts integrated with a complete RRAM circuit design. The controller automates and manages all simulation procedures, while the circuit design comprises a 1T-1R memory array along with essential peripheral components such as write drivers and sense amplifiers. To achieve fast and accurate electrical simulations, we introduce two compact models for RRAMs. These models are optimized and calibrated using extensive measurement data from RRAM devices. We further calibrate the model with industrial measurements from ST Microelectronics. It enables robust device/circuit co-design, accounting for PVT variations and ensuring the reliability and efficiency of RRAM systems..... ... Read more

From the first spark of inspiration to the final forward-looking horizon, this thesis unfolds as a journey to re-imagine the foundations of computation. We merge breakthroughs in materials science, electronic device engineering, and deep generative learning to confront three of modern computing grandest challenges: the energy inefficiencies of classical architectures, the scaling limitations of neuromorphic hardware, and the exponential complexity of quantum systems.

We begin by identifying a threefold bottleneck at the heart of contemporary information processing. On one hand, the von Neumann architecture separates memory from logic, incurring high energy and latency costs. On another, quantum systems, with their exponentially expanding state spaces, defy conventional methods of characterization and control. Bridging these extremes demands both new materials and new paradigms: architectures that think and learn within memory itself and operate seamlessly across room-temperature and cryogenic domains. Our mission is to forge a unified computing framework that fuses neuromorphic principles, cryogenic and room-temperature memristors, and machine intelligence with quantum state tomography (QST).

The conceptual groundwork follows. Inspired by biological neurons, we explore how computation and memory can coexist within memristive architectures. Memristors, particularly resistive switching devices such as HfO2-based ReRAM, emulate synaptic plasticity, enabling analog tuning and in-memory processing. We investigate both spiking and non-spiking neural models, contextualizing their use in QST. The core idea of computation-in-memory (CiM) emerges, performing neural operations directly within dense memristor crossbars, bypassing the von Neumann bottleneck. This unifying concept becomes the architectural backbone of our hybrid classical–quantum platform.

Our theoretical framework spans silicon physics, memristive mechanisms, and the formalism of quantum state reconstruction. We dissect electron-beam-induced processing (EBIP) as a route to room-temperature silicon device fabrication. We examine the physics of OxReRAM switching, ion migration, interfacial engineering, and energy barriers, and we extend this understanding to cryogenic regimes. In parallel, we articulate the formal structure of QST, density matrices, POVMs, and data scaling as 4^N for N qubits, where neural networks emerge as natural generative or inference engines. Variational autoencoders, especially spiking VAEs (SVAEs), form the probabilistic bridge between neuromorphic learning and quantum reconstruction. The materials narrative begins with innovation in silicon processing. Abandoning high-temperature furnaces, we deploy spin-coated liquid polysilanes and transform them into functional amorphous silicon films via focused EBIP. STEM–EELS imaging, residual-gas analysis, and electrical characterization confirm uniform, low-defect films exhibiting stable ohmic behavior over months. This approach enables nanoscale precision and compatibility with flexible substrates, key for next-generation neuromorphic hardware.

ReRAM devices, long hampered by high-voltage electroforming and poor uniformity, are re-engineered. By designing Pd/HfO2 interfaces, we realize forming-free OxReRAM cells that switch at sub-2V, support multibit states, and retain data over 10^4 s. Atomic-scale analysis reveals a Pd–O–Hf interfacial layer that stabilizes low-bias conductive pathways. These devices achieve endurance and energy consumption in the picojoule range, validating them as efficient synaptic elements for in-memory computing. At cryogenic temperatures, the same memristive principles enable a new frontier: Cryo-Memristors for spin-qubit control. Operating reliably at 4 K, Pt/Ti/HfO2-based memristors and their modified variants (M-PtHT) serve as low-noise, multi-bit programmable gain elements for scalable quantum control electronics. Embedded near the quantum layer, these devices synthesize analog bias voltages with sub-100\,µV resolution, drastically reducing the wiring complexity, heat load, and latency in large-scale qubit arrays. Statistical analysis shows linear resistance variation and stable multi-bit retention even at 4\,K, confirming their potential as cryogenic analog memory elements for autonomous qubit tuning and adaptive quantum feedback. This chapter bridges device physics and quantum hardware, demonstrating that memristive programmability can extend beyond neuromorphic computing into the quantum domain.

We confront QST through the lens of machine learning. A diverse suite of neural architectures, FCN, CNN, RNN, RBM, CGAN, and Transformer, is deployed to reconstruct quantum states from simulated measurement data. Among them, CNNs deliver the best trade-off between fidelity and computational time, especially under expectation-based measurements. Yet, the SVAE architecture marks a turning point: as a generative probabilistic model, it achieves high-fidelity reconstructions even under sparse and noisy data, generalizing to higher qubit counts (up to 8) and scaling sub-exponentially in runtime. Its latent-space encoding of high-dimensional quantum information renders it ideal for real-time, energy-efficient inference when implemented on memristive crossbars. Simulations incorporating real device characteristics confirm that our forming-free and cryogenic OxReRAM-based CiM arrays can physically sustain deep QST networks. Memristor crossbars perform rapid in-memory matrix–vector multiplications, reducing inference energy by orders of magnitude compared to digital processors. Together, these results establish a scalable, hardware-aware path toward hybrid classical–neuromorphic–quantum computing.

We conclude by reflecting on the broader implications. This work demonstrates that room-temperature EBIP enables sustainable silicon fabrication; that forming-free OxReRAM devices can be engineered for reliable analog switching; that Cryo-Memristors enable scalable, low-power qubit control; and that generative neural networks, especially SVAEs, offer a pathway to efficient, hardware-embedded quantum state reconstruction. Looking ahead, these innovations converge toward cryogenic integration with quantum processors, adaptive quantum feedback via spiking neuromorphic circuits, and the eventual realization of intelligent, energy-aware quantum systems.

Through every chapter, one theme resounds: the dissolution of boundaries, between memory and logic, between classical and quantum, between matter and model. This thesis lays the foundation for a new kind of computing, one that learns like the brain, reasons like a physicist, and computes like the future demands. ... Read more

Neuromorphic architectures are energy efficient architectures for executing spiking neural networks. Current open-source neuromorphic hardware projects are either experimentation platforms (RANC, ODIN) or neural network accelerators (Open-Spike, SNE), there are no direct processing platforms that support AI and ML applications. Seneca-Lite is an open-source RISC-V based multicore neuromorphic platform. The goal of Seneca-Lite is to enable new possibilities for AI and ML applications and foster more collaboration in this field. The platform is intended for research and academic purposes and furthering the field of neuromorphic computing.

The Seneca-Lite platform utilizes the Ibex core, a highly parameterizable open-source 32 bit RISC-V processor. Each core in the Seneca-Lite platform contains a Network On Chip (NoC) router, local memories, network message FIFOs and interconnects. The multi-core platform is designed to facilitate messaging between cores via the NoC. The NoC used in Seneca-Lite is the same as the NoC used in RANC (Reconfigurable Architecture for Neuromorphic Computing). The number of cores in the system is parameterized and can be controlled by the user depending on their need. Since the platform is open-source, many of the internal parameters (Ibex parameters, FIFO parameters etc) can be tweaked by the user as per their target application.

The completed neuromorphic platform is benchmarked for various state-of-the-art applications and compared to other neuromorphic platforms. ... Read more

One-third of patients suffering from chronic epilepsy, which is caused by abnormal brain activity, is drug-resistant. Animal models are widely used to study the mechanisms leading to epilepsy so better drug treatments can be developed for this disease. In such studies, epileptiform activity, assessed by LFP recordings, can be used as a marker for the development and chronification of disease. However, the analysis of LFP recordings is typically done manually, which is time-consuming, subject to observer bias, error-prone, and lacks consistency and efficiency. Therefore, we present a work which developed a new, automated detection and classification method for epileptiform activity, which was tested in the intrahippocampal kainic acid (IHKA) mouse model, a model of human temporal lobe epilepsy. Our method relies on a spike detector using an improved version of the nonlinear energy operator (NEO) in combination with automatic NEO thresholding (ANT). The detected spikes form the basis of epileptiform event detection and classification. The proposed method is implemented in Python as an automated and time-efficient algorithm that can be used in preclinical studies. Epileptiform event detection accuracy was 93.1% and classification accuracy 95.8%. Moreover, the time for analysis of LFP recordings was reduced by 98.8% compared to manual analysis. Additionally, to demonstrate the potential of the algorithm for application in Brain-Machine Interfaces (BMI), we performed a real-time implementation using both an application-specific integrated circuit (ASIC) and a field programmable gate array (FPGA). The FPGA demonstrated the feasibility of real-time implementation, and the ASIC resulted in an area and power efficient chip using the Taiwan semiconductor manufacturing company (TSMC) 45nm library that constitutes a post-layout area of 9114 µm2 and a power usage of 6.11 µW. ... Read more

As technology nodes continue to shrink, more challenges arise in the field of Design for Testability (DfT). Sequential Integrated Circuits (IC) with asynchronous (re)set flip-flops are notorious for producing unwanted reset behaviour during scan-test. Typically the scan flip-flops are restricted to a non-reset state while the shift operation is performed. This can be achieved by inserting an independent test signal in parallel with each local reset port. This ensures that the scan flip-flops are loaded with the correct input data during the shift cycle. However, before the capture cycle is initiated, this test signal must be released as it prohibits the reset logic from being tested with stuck-at-faults. When there are multiple cascading resets present in the design this release can cause glitches to occur. Since the reset ports operate asynchronously, these glitches can also trigger a scan flip-flop to reset, thereby changing the input data. As a result, some chips may be tested with corrupted input data, leading to differences in scan patterns. Consequently, these ICs fail during manufacturing tests and are classified as faulty, leading to yield loss.


By adding DfT to the (re)set port of each flip-flop these glitches can be prevented at the cost of additional hardware. This thesis establishes the conditions that lead to the occurrence of asynchronous (re)set glitches during scan-test. A design rule-based algorithm is proposed that can accurately identify glitchy structures for circuits without reconvergence. As an extension, a simulation-based algorithm is presented that can further classify which (re)set flip-flops can cause a glitch. These algorithms have been tested on two case studies where glitches have been observed. After deploying these algorithms 33% and 71% of the total number of (re)set flip-flops were identified as glitch-free. By only adding additional DfT to these flip-flops the overhead is significantly reduced. This work addresses a significant challenge in minimizing the cost of robust asynchronous scan test. ... Read more

Deep Neural Networks (DNNs) have revolutionized numerous computational fields, from image and speech recognition to autonomous driving and natural language processing. Yet, the substantial computational and energy requirements of DNNs, particularly Convolutional Neural Networks (CNNs), pose significant obstacles to their deployment on resource-constrained edge devices. This thesis presents SPARO, a novel Scalable Sparsity-Aware Event-Driven Architecture designed to overcome these challenges by effectively exploiting sparsity in both neural network weights and activations.
SPARO’s architecture is founded upon a unique event-driven dataflow that harnesses the inherent sparsity of CNNs, thereby reducing computational burden and energy consumption. This dataflow is strategically divided into two distinct phases: the Update Phase and the Fire Phase. During the Update Phase, all computations essential for incoming events are executed, while the Fire Phase is dedicated to applying non-linear activation functions and pooling operations to the output feature maps (OFM). This meticulously designed phased approach streamlines data handling, eliminates redundant computations, and significantly boosts overall processing efficiency.
A cornerstone of SPARO’s innovation is its dynamic weight reuse mechanism, which intelligently maximizes the reuse of weights across multiple events. This significantly reduces the number of weight fetches needed, thereby improving arithmetic intensity. Furthermore, SPARO leverages advanced sparse data representation techniques to minimize memory usage and further enhance computational efficiency.
The efficacy of SPARO is demonstrated through comprehensive evaluations using both synthetic benchmarks and real-world CNN applications, such as gesture recognition and object detection. In the same form-factor, SPARO achieves an impressive 8.5x speedup compared to the baseline Seneca system, delivering real-time performance while consuming only 14% of the energy for the TinyYolo vision task.
... Read more

Memory advances have not kept up with computing demands. Emerging device technology Resistive RAM (RRAM) addresses this by enabling computation-in-memory. However, RRAM suffers from read disturb, limiting viability. While earlier work has had some success in reducing read disturb by switching the read current direction (a bipolar read scheme), the RRAM device eventually degraded. In this work, a reinforcing bipolar read scheme is introduced, which aims to prevent read disturb by reinforcing both HRS and LRS, away from the undefined state. From device-level simulation, this reinforcing behaviour is predicted for V = 0.5, 0.4 and 0.3 V with a fixed switching ratio between time under positive and negative read voltage polarity rsw i tch = 2.5, 2.5 and 2.75, respectively. At V = 0.2 V and V = 0.1 V, it is predicted that no reinforcement scheme exists. The bipolar read scheme found for V = 0.5 V was evaluated in circuit simulation with a sense amplifier. however the HRS and LRS reinforcing behaviour found at device-level could not be replicated. From unipolar read results at circuit level, it was determined no switching ratio exists that reinforces both the HRS and LRS state boundaries as chosen here at RHRS,min = 12.8kΩ and RLRS,max = 4.4kΩ for V = 0.5 V. However, a 5.1x reduction in resistance drift compared to conventional unipolar read was still obtained.
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Motivated by the desire to bring intelligent processing at the Edge, enabling online learning on resource- and latency-constrained embedded devices has become increasingly appealing, as it has the potential to tackle a wide range of challenges: on the one hand, it can deal with on-the-fly adaptation to fast sensor-generated streams of data under changing environments and on the other hand, it can address a variety of challenges associated with offline training in the cloud, such as incurred energy consumption of sensor data transfers and extra memory storage for the training samples, but also data privacy and security concerns. Concurrently, maintaining low-latency and power-efficient inference is paramount for edge AI computing systems, and thus learning/adapting online with minimal incurred overhead is crucial.

In this work, we propose EON-1, an Edge ONline Learning SCNN (Spiking Convolutional Neural Network) processor with 1-bit synaptic weights, 1-spike per neuron and 1-neuron updated per input, which we have benchmarked for both ASIC and FPGA platforms. Our key contribution is proposing a binary and stochastic SDTP rule which, benchmarked in an ASIC node, achieves less than 1% energy overhead for inference. To our knowledge, our solution incurs the least energy overhead for inference, compared to state-of-the-art solutions, showing a better efficiency by at least a factor of 10x. We also report 94% and 77.65% accuracy on the MNIST and Fashion-MNIST classification tasks, and we achieve 0.09pJ/SOP and 1.5pJ/SOP energy efficiency during inference and learning, respectively. We extend our solution to demonstrate a practical use-case of performing inference in real-time UHD videos while coping with streaming data and we showcase 60 FPS UHD video processing. ... Read more

Modern computer application require large amounts of data processing. Traditional computing models involve constant data transfer between memory and processor. This data transfer is a major contributor to high energy consumption. As these applications scale, the energy demand increases. This poses challenges in terms of sustainability and operational costs. Computation In Memory (CIM) integrates processing within the memory. This reduces the need for data transfer between memory and processor. Potential for drastically lowering energy consumption.

CIM macros are often implemented using modified SRAM cells, though recent literature explores memristor-based CIM designs due to the memristor’s low-energy, non-volatile characteristics. However, no comprehensive comparisons between SRAM-based and memristor-based CIM designs exist. While memristor-based designs are hypothesized to be more energy-efficient, this has not yet been proven.

This thesis compares SRAM-based and memristor-based CIM designs to determine which is better suited for CIM applications. This has been achieved by exploring the state of the art of memristive devices, memristor based CIM macros and SRAM based CIM macros. A selection of designs were chosen to compare, including the 1T1R and 8T SRAM design, which are the most popular memristor based and SRAM based CIM designs. The schematics of all the designs were recreated and simulated using as much of the same parameters as possible in all of the designs. A simulation of performing the logic AND and the MAC operation was made. Additionally a layout of the designs was made to extract the area. The designs were compared based on area, energy consumption and delay.

From the results could be concluded that the best device for CIM depends on the application. The memristor design had the smallest area and consumed the least amount of energy for reading, logic and MAC operations. The memristor design also consumed the most amount of energy during writing and the delay for all operations is longer than with the SRAM based designs. If area, energy consumption and delay are equally important for an application, then memristor based CIM would be the better choice only if there are much more logic/read operations than write operations. It could be the better choice for MAC operations if a more energy efficient ADC was used than the one used in this thesis. ... Read more

Machine learning on edge devices performs crucial identification or prediction tasks while limiting the amount of data that needs to be transmitted to more centralized computing nodes. However, strict area and energy requirements necessitate specialized hardware developed for the requirements of the device and model. This thesis is concerned with developing an area and energy arithmetic unit as part of the implementation of a stacked machine learning model in embedded automotive devices. The model in question was previously designed to perform lifetime prediction with the goal of improving the reliability of semiconductor devices used in various automotive applications.

This thesis aims to achieve area and energy efficiency by exploiting the commonalities in the arithmetic operations of several of the internal learners of the stacked machine learning model. The use of a weighted figure of merit, taking into account area, energy and delay, allow for simple comparisons of designs at any operation frequency and easy insight into the changes in the merit of designs if device requirements were to change. A sweep of the percentage of multiplications in the workload also gave insight into how design choices may change due to future redesigns of the stacked machine learning model.

It was found that the MAC, multiply, divide and accumulate operations of the internal learners can best be supported by one arithmetic unit containing a "Reduced Area" parallel multiplier (still taking up most of the area), a small, dedicated accumulator and invariant integer division using the multiplier. It was also found that the ability to reconfigure the multiplier for different levels of bit-precision does not yield performance improvement for the expected precision distribution. ... Read more

Artificial intelligence (AI) is rapidly becoming an integral part of many real-world products and services. This is mainly facilitated by the extensive computing resources provided by the cloud infrastructure. However, cloud-based AI processing suffers from drawbacks like high latency, huge network costs, data privacy/security concerns, and service disruptions due to internet outage. Edge computing for AI (edge-AI) addresses these problems by combining data sources with on-board AI processing hardware. Such hardware must be energy efficient to achieve prolonged operation, given the limited energy resources on edge devices. Moreover, it should be compact in size to facilitate seamless system integration and enhanced portability. Conventional hardware cannot meet these requirements due to data transfer bottleneck in von Neumann architecture and limitations of conventional memory technologies.
Computation-in-memory (CIM) overcomes these challenges by in-situ data processing using emerging memory technologies called memristors. Thus, CIM can facilitate energy efficient and compact edge-AI hardware design. Healthcare domain stands out as a prime target for CIM-based edge-AI hardware, due to two main reasons. Firstly, it holds significant real-world importance due to its direct impact on human well-being. Secondly, the increasing adoption of AI in healthcare can significantly benefit from efficient hardware for data processing. CIM-based edge hardware can greatly enhance the effectiveness of AI-based healthcare through rapid, reliable, and secure processing of medical data at its source. Hence, design of CIM-based edge-AI hardware for healthcare applications presents a promising research direction.

The process of designing CIM-based edge-AI hardware for healthcare can be expressed as a stack of six abstraction layers: application, algorithm, optimization, mapping, micro-architecture and circuits, and device. These abstraction layers can be further grouped into two distinct design phases. The first phase is application-dependent, covering the first three abstraction layers (application, algorithm and optimization). It involves creating a customized neural network model for the given healthcare application. The challenge in this phase is to achieve strong algorithmic performance, while incorporating features to exploit the full potential of CIM hardware. Conversely, the second phase is application-independent and comprises of the remaining abstraction layers (mapping, micro-architecture and circuits, and device). It solely focuses on translating the model computations into CIM hardware operations. However, the non-ideal characteristics of memristor devices introduce computational errors in hardware operations. This undermines the advantages of CIM as energy-efficient computations are of no use if they are incorrect. Hence, mitigating memristor non-idealities becomes the primary challenge in this phase. Moreover, it is important to integrate the customized model and non-ideality mitigation strategies into a comprehensive hardware solution and realize it through prototyping. This gives rise to the following three research topics: 1) healthcare AI models for CIM-based edge hardware, 2) dealing with memristor non-idealities, and 3) CIM edge-AI prototyping for healthcare.

We adopt a cross-layer approach in this thesis to address these research topics, covering all six layers of the CIM abstraction stack. We begin by creating neural network models for two healthcare applications: cardiac arrhythmia classification and diabetic retinopathy screening. Our contributions in this application-dependent design phase span across the first three abstraction layers (application, algorithm and optimization). At the application layer, we introduce new features in the model tailored to the specific healthcare application. This enhances its real-world impact by addressing the unique medical needs more effectively. Moving to the algorithm layer, we customize the computational flow within the model to exploit the characteristics of the healthcare data. This improves design performance in key aspects like accuracy and energy efficiency. Moreover, we strategically refine the model computations to further maximize post-deployment benefits on CIM hardware. At the optimization layer, we employ techniques like resampling, quantization and pruning to optimize hardware resource requirements, without compromising the model's algorithmic performance.

After creating the neural network models, we proceed to the application-independent design phase. Focusing on RRAM-based memristor devices, we first identify three key non-idealities that significantly impact inference accuracy on CIM hardware. We then devise mitigation strategies against these non-idealities, encompassing the remaining abstraction layers (mapping, micro-architecture and circuits, and device). At mapping layer, we propose a hardware-aware training methodology to combat the conductance variation non-ideality. Moving to the micro-architecture level, we present two mitigation strategies. The first addresses non-zero Gmin error non-ideality through a novel approach to CIM micro-architecture design. The second introduces an adaptive micro-architecture that adjusts its sensing conditions to counteract the effects of read-disturb non-ideality. At the device level, these strategies indirectly contribute by circumventing the necessity for extensive device engineering, ensuring accurate inference even in the presence of non-idealities. Building upon this foundation of model development and non-ideality mitigation, we integrate the optimal ECG classification model with the proposed mitigation strategies to create a CIM edge-AI prototype. Thus, our contributions pave the way towards a future with enhanced effectiveness and efficiency of AI-powered healthcare. ... Read more

The security of electronic devices holds the greatest importance in the modern digital era, with one of the emerging challenges being the widespread occurrence of hardware attacks. The aforementioned attacks present a substantial risk to hardware devices, and it is of utmost importance to comprehend the potential detrimental effects they may cause. Side-channel attacks are a class of hardware attacks that exploit information unintentionally leaked by a device during its operation. These leaks manifest in various forms, including power consumption, time variations, and thermal dissipation. The fundamental danger posed by side-channel attacks is their ability to infer sensitive information from these unintended emissions. To address the heightened risks associated with side-channel attacks, this thesis focuses on three main research topics. ... Read more