Event-driven neural network accelerators achieve superior energy efficiency by processing only meaningful data events, yet existing design space exploration tools lack support for their asynchronous execution characteristics. This thesis introduces AeDAM (Event-Driven Architecture Mapping), a specialized framework for systematic exploration of event-driven accelerator architectures.

AeDAM transforms traditional synchronous mapping methodologies into event-driven configurations through intelligent Loop Order Memory Access scheduling and specialized analytical cost models for asynchronous dataflows, targeting energy-delay product optimization.
Experimental validation using the SENECA neuromorphic architecture demonstrates substantial improvements: 2.5× faster exploration times, 13-52% latency reductions across VGGNet layers, and 12× energy-delay product improvements. Optimal configurations feature 512KB SRAM capacity and multi-dimensional processing element arrays.

AeDAM establishes a foundation for systematic exploration of energy-efficient event driven computing systems targeting edge applications.