As technology nodes continue to shrink, more challenges arise in the field of Design for Testability (DfT). Sequential Integrated Circuits (IC) with asynchronous (re)set flip-flops are notorious for producing unwanted reset behaviour during scan-test. Typically the scan flip-flops are restricted to a non-reset state while the shift operation is performed. This can be achieved by inserting an independent test signal in parallel with each local reset port. This ensures that the scan flip-flops are loaded with the correct input data during the shift cycle. However, before the capture cycle is initiated, this test signal must be released as it prohibits the reset logic from being tested with stuck-at-faults. When there are multiple cascading resets present in the design this release can cause glitches to occur. Since the reset ports operate asynchronously, these glitches can also trigger a scan flip-flop to reset, thereby changing the input data. As a result, some chips may be tested with corrupted input data, leading to differences in scan patterns. Consequently, these ICs fail during manufacturing tests and are classified as faulty, leading to yield loss.


By adding DfT to the (re)set port of each flip-flop these glitches can be prevented at the cost of additional hardware. This thesis establishes the conditions that lead to the occurrence of asynchronous (re)set glitches during scan-test. A design rule-based algorithm is proposed that can accurately identify glitchy structures for circuits without reconvergence. As an extension, a simulation-based algorithm is presented that can further classify which (re)set flip-flops can cause a glitch. These algorithms have been tested on two case studies where glitches have been observed. After deploying these algorithms 33% and 71% of the total number of (re)set flip-flops were identified as glitch-free. By only adding additional DfT to these flip-flops the overhead is significantly reduced. This work addresses a significant challenge in minimizing the cost of robust asynchronous scan test.

Epilepsy is a medical condition which is caused by excessive or synchronous neuronal activity of the brain cells. These activities can lead to attacks where the patient can lose conciseness or experiences random muscle cramps at seemingly any point in time. Using implantable on body sensors these seizure attacks could be detected and even prevented. These sensors would form a Medical Body Area Network (MBAN) which interconnects all of the sensors. This project looks at a proof of concept implementation of such an MBAN and focuses on a secure connection between an implant and a gateway device, which is a mobile phone. The implant and mobile phone will communicate with each other using Bluetooth Low Energy (BLE). This form of communication does not provide a secure pairing method for devices that lack in- and output capabilities, such as an implant. To set up a secure connection the data will be encrypted with an encryption key, which has to be shared between the implant and mobile phone. In order to do this in a secure way, an Out Of Band (OOB) channel will be used to pair the two devices. This thesis looks at three different OOB channels, Near Field Communication (NFC), ultrasound and galvanic coupling and compares them in therms of security, health safety, data rate, power consumption and feasibility.