BCIM

Efficient Implementation of Binary Neural Network Based on Computation in Memory

Journal Article (2024)
Author(s)

Mahdi Zahedi (TU Delft - Computer Engineering)

Taha Shahroodi (TU Delft - Computer Engineering)

Carlos Escuin (Universidad de Zaragoza)

Georgi Gaydadjiev (TU Delft - Quantum Circuit Architectures and Technology, Imperial College London)

S. Wong (TU Delft - Computer Engineering)

S. Hamdioui (TU Delft - Computer Engineering)

Research Group
Computer Engineering
DOI related publication
https://doi.org/10.1109/TETC.2024.3406628
More Info
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Publication Year
2024
Language
English
Research Group
Computer Engineering
Bibliographical Note
Green Open Access added to TU Delft Institutional Repository as part of the Taverne amendment. More information about this copyright law amendment can be found at https://www.openaccess.nl. Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public. @en
Issue number
2
Volume number
13
Pages (from-to)
395-408
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Abstract

Applications of Binary Neural Networks (BNNs) are promising for embedded systems with hard constraints on energy and computing power. Contrary to conventional neural networks using floating-point datatypes, BNNs use binarized weights and activations to reduce memory and computation requirements. Memristors, emerging non-volatile memory devices, show great potential as a target implementation platform for BNNs by integrating storage and compute units. However, the efficiency of this hardware highly depends on how the network is mapped and executed on these devices. In this paper, we propose an efficient implementation of XNOR-based BNN to maximize parallelization. In this implementation, costly analog-to-digital converters are replaced with sense amplifiers with custom reference(s) to generate activation values. Besides, a novel mapping is introduced to minimize the overhead of data communication between convolution layers mapped to different memristor crossbars. This comes with extensive analytical and simulation-based analysis to evaluate the implication of different design choices considering the accuracy of the network. The results show that our approach achieves up to 5× energy-saving and 100× improvement in latency compared to baselines.

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