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A.R. Mohammad Zaki
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Imaging nanoscopic features with Scanning Electron Microscopes (SEMs) requires rapid specimen scanning with a low-energy electron beam. The electron detector is highly pixelated. Each pixel is interfaced with a high-precision, widebandwidth, low-noise readout integrated circuit (ROIC), to enable single-electron counting operation. This paper introduces an innovative power-efficient pixel readout frontend architecture, achieving a time resolution of 2.5 ns. The fabricated prototype in 40 nm CMOS process demonstrates better than 6 ppm electron detection precision. It consumes only 200 μ W, with an area of 150 μ m × 100 μ m.
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Imaging nanoscopic features with Scanning Electron Microscopes (SEMs) requires rapid specimen scanning with a low-energy electron beam. The electron detector is highly pixelated. Each pixel is interfaced with a high-precision, widebandwidth, low-noise readout integrated circuit (ROIC), to enable single-electron counting operation. This paper introduces an innovative power-efficient pixel readout frontend architecture, achieving a time resolution of 2.5 ns. The fabricated prototype in 40 nm CMOS process demonstrates better than 6 ppm electron detection precision. It consumes only 200 μ W, with an area of 150 μ m × 100 μ m.
This Ph.D. dissertation focuses on designing high-precision readout frontends for low energy charge detection in scanning electron microscopy (SEM), achieving a time resolution of 2.5 ns, a detection error rate below 6 ppm, and power consumption under 400 μW. Novel techniques at both the system and circuit levels were developed to enhance operational accuracy and meet the target specifications. Two prototypes were presented and experimentally tested to demonstrate the effectiveness of these techniques.
Chapter 1 introduces the motivation, research objectives, and organization of the thesis, highlighting the advancements in SEMs for nanometer-resolution imaging and the challenges posed by high scanning speeds. It emphasizes the need for sensitive detectors and low-noise, power-efficient readout electronics, which often conflict. The main research question is defined as developing a frontend readout architecture with power consumption below 500 μW, time resolution of 2.5 ns, and an electron count error under 10 ppm. To address this, the thesis employs a systematic study and iterative design process, resulting in two novel readout frontend architectures. The chapter also outlines the structure of the thesis, covering the operating principles of the PIN diode, design details, experimental evaluations, and conclusions.
Chapter 2 provides a detailed review of the target application specifications, focusing on the design and requirements for detecting weak charge signals with high precision and time resolution. It critically analyzes the current state-of-the-art readout frontends, highlighting their strengths and inherent limitations, particularly in terms of noise performance, time resolution, and power consumption. This chapter also introduces the concept of short and open circuit readout modes for PIN-diodes, offering insights into their potential advantages for addressing the challenges identified in the existing systems.
Chapter 3 presents the design of readout solutions for the short circuit operation mode of PIN-diodes, critical for BSE detection in electron microscopy. It examines the use of a preamplifier to create a virtual ground, effectively simulating a zero-impedance load and ensuring accurate charge transfer. The chapter further explores the analog frontend components: preamplifier, signal shaping filters, and threshold discriminators. Signal shaping filters, both passive and active high-pass types, are discussed for their role in signal optimization by reducing noise and improving signal clarity. Additionally, the threshold discriminator design is analyzed for both filter types, emphasizing the importance of accurate signal discrimination to minimize detection errors. A key focus is the tradeoff between power consumption, noise performance, and detection accuracy, with each stage's design detailed to ensure optimal performance and signal integrity in the short circuit mode.
Chapter 4 explores readout solutions for the open circuit mode of PIN-diodes, focusing on high sensitivity, low power consumption, and signal integrity. It highlights challenges like charge pileup and saturation, proposing solutions such as a reset mechanism and dynamic comparators. The chapter discusses an advanced frontend architecture with offset compensation and active capacitor matching for improved accuracy. Periodic sampling at 800 MHz minimizes timing misalignments, balancing power efficiency and reliability for high-resolution, high-rate applications.
Chapter 5 discusses the experimental setup and qualification of the proposed readout architectures. The device under test (DUT), a 40 nm CMOS chip with short and open circuit mode readout matrices, is tested to validate its ability to detect and digitize charge signals within the specified power budget. The test includes evaluating performance across gain, noise, bandwidth, and threshold levels, using a programmable detector emulating circuit (DEC) to simulate charge signals. The setup features a FPGA-based Data Acquisition Board (DAB) for signal monitoring and a test PCB to run experimental qualifications.
Chapter 6 concludes the thesis by highlighting the development of advanced readout frontends for high-precision charge detection, achieving improved time resolution, accuracy, and power efficiency. The proposed designs, optimized for short circuit and open circuit modes, demonstrate excellent performance. This chapter also proposes and discusses some aspects of this work that could be explored for further improvements. ...
Chapter 1 introduces the motivation, research objectives, and organization of the thesis, highlighting the advancements in SEMs for nanometer-resolution imaging and the challenges posed by high scanning speeds. It emphasizes the need for sensitive detectors and low-noise, power-efficient readout electronics, which often conflict. The main research question is defined as developing a frontend readout architecture with power consumption below 500 μW, time resolution of 2.5 ns, and an electron count error under 10 ppm. To address this, the thesis employs a systematic study and iterative design process, resulting in two novel readout frontend architectures. The chapter also outlines the structure of the thesis, covering the operating principles of the PIN diode, design details, experimental evaluations, and conclusions.
Chapter 2 provides a detailed review of the target application specifications, focusing on the design and requirements for detecting weak charge signals with high precision and time resolution. It critically analyzes the current state-of-the-art readout frontends, highlighting their strengths and inherent limitations, particularly in terms of noise performance, time resolution, and power consumption. This chapter also introduces the concept of short and open circuit readout modes for PIN-diodes, offering insights into their potential advantages for addressing the challenges identified in the existing systems.
Chapter 3 presents the design of readout solutions for the short circuit operation mode of PIN-diodes, critical for BSE detection in electron microscopy. It examines the use of a preamplifier to create a virtual ground, effectively simulating a zero-impedance load and ensuring accurate charge transfer. The chapter further explores the analog frontend components: preamplifier, signal shaping filters, and threshold discriminators. Signal shaping filters, both passive and active high-pass types, are discussed for their role in signal optimization by reducing noise and improving signal clarity. Additionally, the threshold discriminator design is analyzed for both filter types, emphasizing the importance of accurate signal discrimination to minimize detection errors. A key focus is the tradeoff between power consumption, noise performance, and detection accuracy, with each stage's design detailed to ensure optimal performance and signal integrity in the short circuit mode.
Chapter 4 explores readout solutions for the open circuit mode of PIN-diodes, focusing on high sensitivity, low power consumption, and signal integrity. It highlights challenges like charge pileup and saturation, proposing solutions such as a reset mechanism and dynamic comparators. The chapter discusses an advanced frontend architecture with offset compensation and active capacitor matching for improved accuracy. Periodic sampling at 800 MHz minimizes timing misalignments, balancing power efficiency and reliability for high-resolution, high-rate applications.
Chapter 5 discusses the experimental setup and qualification of the proposed readout architectures. The device under test (DUT), a 40 nm CMOS chip with short and open circuit mode readout matrices, is tested to validate its ability to detect and digitize charge signals within the specified power budget. The test includes evaluating performance across gain, noise, bandwidth, and threshold levels, using a programmable detector emulating circuit (DEC) to simulate charge signals. The setup features a FPGA-based Data Acquisition Board (DAB) for signal monitoring and a test PCB to run experimental qualifications.
Chapter 6 concludes the thesis by highlighting the development of advanced readout frontends for high-precision charge detection, achieving improved time resolution, accuracy, and power efficiency. The proposed designs, optimized for short circuit and open circuit modes, demonstrate excellent performance. This chapter also proposes and discusses some aspects of this work that could be explored for further improvements. ...
This Ph.D. dissertation focuses on designing high-precision readout frontends for low energy charge detection in scanning electron microscopy (SEM), achieving a time resolution of 2.5 ns, a detection error rate below 6 ppm, and power consumption under 400 μW. Novel techniques at both the system and circuit levels were developed to enhance operational accuracy and meet the target specifications. Two prototypes were presented and experimentally tested to demonstrate the effectiveness of these techniques.
Chapter 1 introduces the motivation, research objectives, and organization of the thesis, highlighting the advancements in SEMs for nanometer-resolution imaging and the challenges posed by high scanning speeds. It emphasizes the need for sensitive detectors and low-noise, power-efficient readout electronics, which often conflict. The main research question is defined as developing a frontend readout architecture with power consumption below 500 μW, time resolution of 2.5 ns, and an electron count error under 10 ppm. To address this, the thesis employs a systematic study and iterative design process, resulting in two novel readout frontend architectures. The chapter also outlines the structure of the thesis, covering the operating principles of the PIN diode, design details, experimental evaluations, and conclusions.
Chapter 2 provides a detailed review of the target application specifications, focusing on the design and requirements for detecting weak charge signals with high precision and time resolution. It critically analyzes the current state-of-the-art readout frontends, highlighting their strengths and inherent limitations, particularly in terms of noise performance, time resolution, and power consumption. This chapter also introduces the concept of short and open circuit readout modes for PIN-diodes, offering insights into their potential advantages for addressing the challenges identified in the existing systems.
Chapter 3 presents the design of readout solutions for the short circuit operation mode of PIN-diodes, critical for BSE detection in electron microscopy. It examines the use of a preamplifier to create a virtual ground, effectively simulating a zero-impedance load and ensuring accurate charge transfer. The chapter further explores the analog frontend components: preamplifier, signal shaping filters, and threshold discriminators. Signal shaping filters, both passive and active high-pass types, are discussed for their role in signal optimization by reducing noise and improving signal clarity. Additionally, the threshold discriminator design is analyzed for both filter types, emphasizing the importance of accurate signal discrimination to minimize detection errors. A key focus is the tradeoff between power consumption, noise performance, and detection accuracy, with each stage's design detailed to ensure optimal performance and signal integrity in the short circuit mode.
Chapter 4 explores readout solutions for the open circuit mode of PIN-diodes, focusing on high sensitivity, low power consumption, and signal integrity. It highlights challenges like charge pileup and saturation, proposing solutions such as a reset mechanism and dynamic comparators. The chapter discusses an advanced frontend architecture with offset compensation and active capacitor matching for improved accuracy. Periodic sampling at 800 MHz minimizes timing misalignments, balancing power efficiency and reliability for high-resolution, high-rate applications.
Chapter 5 discusses the experimental setup and qualification of the proposed readout architectures. The device under test (DUT), a 40 nm CMOS chip with short and open circuit mode readout matrices, is tested to validate its ability to detect and digitize charge signals within the specified power budget. The test includes evaluating performance across gain, noise, bandwidth, and threshold levels, using a programmable detector emulating circuit (DEC) to simulate charge signals. The setup features a FPGA-based Data Acquisition Board (DAB) for signal monitoring and a test PCB to run experimental qualifications.
Chapter 6 concludes the thesis by highlighting the development of advanced readout frontends for high-precision charge detection, achieving improved time resolution, accuracy, and power efficiency. The proposed designs, optimized for short circuit and open circuit modes, demonstrate excellent performance. This chapter also proposes and discusses some aspects of this work that could be explored for further improvements.
Chapter 1 introduces the motivation, research objectives, and organization of the thesis, highlighting the advancements in SEMs for nanometer-resolution imaging and the challenges posed by high scanning speeds. It emphasizes the need for sensitive detectors and low-noise, power-efficient readout electronics, which often conflict. The main research question is defined as developing a frontend readout architecture with power consumption below 500 μW, time resolution of 2.5 ns, and an electron count error under 10 ppm. To address this, the thesis employs a systematic study and iterative design process, resulting in two novel readout frontend architectures. The chapter also outlines the structure of the thesis, covering the operating principles of the PIN diode, design details, experimental evaluations, and conclusions.
Chapter 2 provides a detailed review of the target application specifications, focusing on the design and requirements for detecting weak charge signals with high precision and time resolution. It critically analyzes the current state-of-the-art readout frontends, highlighting their strengths and inherent limitations, particularly in terms of noise performance, time resolution, and power consumption. This chapter also introduces the concept of short and open circuit readout modes for PIN-diodes, offering insights into their potential advantages for addressing the challenges identified in the existing systems.
Chapter 3 presents the design of readout solutions for the short circuit operation mode of PIN-diodes, critical for BSE detection in electron microscopy. It examines the use of a preamplifier to create a virtual ground, effectively simulating a zero-impedance load and ensuring accurate charge transfer. The chapter further explores the analog frontend components: preamplifier, signal shaping filters, and threshold discriminators. Signal shaping filters, both passive and active high-pass types, are discussed for their role in signal optimization by reducing noise and improving signal clarity. Additionally, the threshold discriminator design is analyzed for both filter types, emphasizing the importance of accurate signal discrimination to minimize detection errors. A key focus is the tradeoff between power consumption, noise performance, and detection accuracy, with each stage's design detailed to ensure optimal performance and signal integrity in the short circuit mode.
Chapter 4 explores readout solutions for the open circuit mode of PIN-diodes, focusing on high sensitivity, low power consumption, and signal integrity. It highlights challenges like charge pileup and saturation, proposing solutions such as a reset mechanism and dynamic comparators. The chapter discusses an advanced frontend architecture with offset compensation and active capacitor matching for improved accuracy. Periodic sampling at 800 MHz minimizes timing misalignments, balancing power efficiency and reliability for high-resolution, high-rate applications.
Chapter 5 discusses the experimental setup and qualification of the proposed readout architectures. The device under test (DUT), a 40 nm CMOS chip with short and open circuit mode readout matrices, is tested to validate its ability to detect and digitize charge signals within the specified power budget. The test includes evaluating performance across gain, noise, bandwidth, and threshold levels, using a programmable detector emulating circuit (DEC) to simulate charge signals. The setup features a FPGA-based Data Acquisition Board (DAB) for signal monitoring and a test PCB to run experimental qualifications.
Chapter 6 concludes the thesis by highlighting the development of advanced readout frontends for high-precision charge detection, achieving improved time resolution, accuracy, and power efficiency. The proposed designs, optimized for short circuit and open circuit modes, demonstrate excellent performance. This chapter also proposes and discusses some aspects of this work that could be explored for further improvements.
State-of-the-art readout integrated circuits (ROICs) operating in particle-counting mode are tending toward high time resolution in the nanosecond range, low-noise for accurate detection of lower-energy particles, and low-power consumption allowing the use of multiple channels on a single die. In previous reports we have presented a particle counting ROIC comprising: a charge-sensitive amplifier (CSA), an active shaping filter, and a discriminator. The use of an active shaping filter provides additional gain for the signal, which relaxes the requirements for the discriminator and makes it more power-efficient. At the same time, the active shaping filter itself consumes a considerable amount of power to operate properly. In this paper we present an alternative solution, based on the same architecture, in which the active shaping filter is replaced by a passive high-pass RC filter with no static power consumption. The price to pay is increased power consumption of a more advanced discriminator with periodic offset compensation. Nevertheless, we report a comparable performance of the two solutions with a 32% overall power reduction with the passive RC filter. The design is made for TSMC 40nm MS/RF CMOS technology.
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State-of-the-art readout integrated circuits (ROICs) operating in particle-counting mode are tending toward high time resolution in the nanosecond range, low-noise for accurate detection of lower-energy particles, and low-power consumption allowing the use of multiple channels on a single die. In previous reports we have presented a particle counting ROIC comprising: a charge-sensitive amplifier (CSA), an active shaping filter, and a discriminator. The use of an active shaping filter provides additional gain for the signal, which relaxes the requirements for the discriminator and makes it more power-efficient. At the same time, the active shaping filter itself consumes a considerable amount of power to operate properly. In this paper we present an alternative solution, based on the same architecture, in which the active shaping filter is replaced by a passive high-pass RC filter with no static power consumption. The price to pay is increased power consumption of a more advanced discriminator with periodic offset compensation. Nevertheless, we report a comparable performance of the two solutions with a 32% overall power reduction with the passive RC filter. The design is made for TSMC 40nm MS/RF CMOS technology.
Accurate registration of weak charge signals with a high event rate is the most challenging requirement of state-of-the-art detector readout frontends. This has given rise to the development of a wide variety of low-noise power-efficient readout frontends with a trend in achieving an ultra-small detection error and small silicon area occupation. This paper presents the methodology and experimental characterization of a state-of-the-art particle detection ROIC (readout integrated circuit) employing an active shaper after the frontend charge-sensitive amplifier (CSA), with: high time resolution (2.5 ns), low-noise, and very good power-efficiency, for registering charge signals between 140 aC and 200 aC, resulting from particles impinging in a silicon PIN detector. The small silicon area occupation of the readout electronic circuit allows a small detector area, which, in backside illumination/exposure mode, provides the opportunity for the pixelization of the total detector area with close to a 100 % fill factor. Experimental verification tests indicate that the proposed ROIC, designed in TSMC 40 nm MS/RF CMOS technology, operates with 3-sigma error rates between 1.8 ppm and 1.3 ppm (parts per million), with the above-mentioned charge signal range, provided that no more than one particle hits the detector surface in a 2.5 ns period of time. The power consumption is 0.37 mW.
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Accurate registration of weak charge signals with a high event rate is the most challenging requirement of state-of-the-art detector readout frontends. This has given rise to the development of a wide variety of low-noise power-efficient readout frontends with a trend in achieving an ultra-small detection error and small silicon area occupation. This paper presents the methodology and experimental characterization of a state-of-the-art particle detection ROIC (readout integrated circuit) employing an active shaper after the frontend charge-sensitive amplifier (CSA), with: high time resolution (2.5 ns), low-noise, and very good power-efficiency, for registering charge signals between 140 aC and 200 aC, resulting from particles impinging in a silicon PIN detector. The small silicon area occupation of the readout electronic circuit allows a small detector area, which, in backside illumination/exposure mode, provides the opportunity for the pixelization of the total detector area with close to a 100 % fill factor. Experimental verification tests indicate that the proposed ROIC, designed in TSMC 40 nm MS/RF CMOS technology, operates with 3-sigma error rates between 1.8 ppm and 1.3 ppm (parts per million), with the above-mentioned charge signal range, provided that no more than one particle hits the detector surface in a 2.5 ns period of time. The power consumption is 0.37 mW.
This paper presents a thorough investigation and evaluation of readout Application-Specific Integrated Circuits (ASICs) tailored for Backscattered Electron (BSE) detection in electron microscopy. The study explores the architecture, operational principles, and performance assessment of integrating and electron counting systems utilized for signal processing in BSE detection. Evaluation of the count rate capability of the readout ASICs is undertaken under diverse conditions, considering variables such as BSE energy, discriminator threshold levels, and preamplifier characteristics. Detailed methodologies for experimental qualification, including test setups, trigger mechanisms, and count rate capability assessments, are outlined to ensure precise evaluation of the ASIC performance. The novel readout ASICs are compared by assessing their maximum output count rate capabilities. Furthermore, we propose strategies to enhance the output count rate by preventing preamplifier saturation, providing insights into the challenges and methods for achieving high-flux rate BSE detection. Experimental verifications validate the effectiveness of the proposed strategies and assessment methodologies in achieving high detection accuracy.
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This paper presents a thorough investigation and evaluation of readout Application-Specific Integrated Circuits (ASICs) tailored for Backscattered Electron (BSE) detection in electron microscopy. The study explores the architecture, operational principles, and performance assessment of integrating and electron counting systems utilized for signal processing in BSE detection. Evaluation of the count rate capability of the readout ASICs is undertaken under diverse conditions, considering variables such as BSE energy, discriminator threshold levels, and preamplifier characteristics. Detailed methodologies for experimental qualification, including test setups, trigger mechanisms, and count rate capability assessments, are outlined to ensure precise evaluation of the ASIC performance. The novel readout ASICs are compared by assessing their maximum output count rate capabilities. Furthermore, we propose strategies to enhance the output count rate by preventing preamplifier saturation, providing insights into the challenges and methods for achieving high-flux rate BSE detection. Experimental verifications validate the effectiveness of the proposed strategies and assessment methodologies in achieving high detection accuracy.
State-of-the-art readout integrated circuits (ROICs) operating in particle-counting mode are gravitating toward high time resolution, low-noise, and low-power analog readout frontends to detect and register the arrival time of charge signals with a high accuracy. To achieve a time resolution of a few nanoseconds, an intermediate stage, known as a signal shaper block, is the preferred solution in the readout frontend, as it compensates for the inter-symbol interference-induced errors by realizing a band-pass transfer function. This paper presents the design methodology and experimental characterization of a state-of-the-art, high time resolution, low-offset, and power-efficient band-pass signal shaper block intended for fitting the voltage signals generated by a charge-sensitive amplifier (CSA) as a function of charge signals as small as 160 aC, into timeframes of 2.5 ns with 17 times offset attenuation while consuming 0.17 mW of power. Detailed information about the operation principle of this CSA, designed in TSMC 40 nm MS/RF CMOS technology, is reported in a previous publication.
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State-of-the-art readout integrated circuits (ROICs) operating in particle-counting mode are gravitating toward high time resolution, low-noise, and low-power analog readout frontends to detect and register the arrival time of charge signals with a high accuracy. To achieve a time resolution of a few nanoseconds, an intermediate stage, known as a signal shaper block, is the preferred solution in the readout frontend, as it compensates for the inter-symbol interference-induced errors by realizing a band-pass transfer function. This paper presents the design methodology and experimental characterization of a state-of-the-art, high time resolution, low-offset, and power-efficient band-pass signal shaper block intended for fitting the voltage signals generated by a charge-sensitive amplifier (CSA) as a function of charge signals as small as 160 aC, into timeframes of 2.5 ns with 17 times offset attenuation while consuming 0.17 mW of power. Detailed information about the operation principle of this CSA, designed in TSMC 40 nm MS/RF CMOS technology, is reported in a previous publication.
Small charge detection is used for a wide range of applications: advanced industrial process control, experimental physics and space instruments, and material testing and medical imaging. These applications give rise to the development of a wide variety of charge-sensitive readout integrated circuits (ROICs). The trend in the state-of-the-art systems is to design low-noise and low-power readout electronics with a low detection error rate and small silicon area occupation, allowing the pixelization of the detector area. This paper presents the methodology and the test setup for the challenging experimental characterization of a state-of-the-art, high time-resolution, low-noise, power-efficient, charge-sensitive ROIC intended for counting single particles detected by a silicon PIN detector. The ROIC is designed to detect charge portions as small as 160 aC, with 0.14 mW power consumption. For every charge pulse of the detector, the ROIC generates voltage signals with a peak amplitude of 29.45 mV, a rise time of 2.56 ns, and an SNR above 20. Detailed information about the operation principle of this ROIC, designed in TSMC 40-nm MS/RF CMOS technology, is reported in a previous publication.
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Small charge detection is used for a wide range of applications: advanced industrial process control, experimental physics and space instruments, and material testing and medical imaging. These applications give rise to the development of a wide variety of charge-sensitive readout integrated circuits (ROICs). The trend in the state-of-the-art systems is to design low-noise and low-power readout electronics with a low detection error rate and small silicon area occupation, allowing the pixelization of the detector area. This paper presents the methodology and the test setup for the challenging experimental characterization of a state-of-the-art, high time-resolution, low-noise, power-efficient, charge-sensitive ROIC intended for counting single particles detected by a silicon PIN detector. The ROIC is designed to detect charge portions as small as 160 aC, with 0.14 mW power consumption. For every charge pulse of the detector, the ROIC generates voltage signals with a peak amplitude of 29.45 mV, a rise time of 2.56 ns, and an SNR above 20. Detailed information about the operation principle of this ROIC, designed in TSMC 40-nm MS/RF CMOS technology, is reported in a previous publication.
This paper presents the design methodology, test setup and experimental qualification results of a high-speed low-power threshold comparator in 40 nm CMOS technology intended for the registry of particles landing on a PIN-detector surface in particle detector readout electronics. The operation of the designed comparator is experimentally qualified for ideal digital pulses and analog signals generated by the preceding stages in a targeted potential application.
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This paper presents the design methodology, test setup and experimental qualification results of a high-speed low-power threshold comparator in 40 nm CMOS technology intended for the registry of particles landing on a PIN-detector surface in particle detector readout electronics. The operation of the designed comparator is experimentally qualified for ideal digital pulses and analog signals generated by the preceding stages in a targeted potential application.
This article presents the experimentally characterized performance of a low noise and wideband sensor readout integrated circuit (ROIC). The ROIC is designed to detect small amounts of charge generated by a silicon p-i-n detector as a result of particle detection, with very high time resolution and limited power consumption. The architecture of the ROIC permits the analog components of the particle readout to be designed with a reduced bandwidth by implementing the so-called intersymbol interference (ISI) cancellation technique, which improves the noise performance, while reducing the deterministic ISI-induced errors associated with the narrowband circuit; hence, a low error rate (ER) can be maintained. The readout is designed to detect 160 aC charge portions delivered randomly by the detector at a maximum of 4 × 108 events/s with a small average ER while consuming 2.85 mW. Detailed information about the ROIC designed in 65-nm CMOS technology, and the simulated performance, are already reported in a previous publication. This article aims to present the challenges related to the design of the test setup and the obtained experimental results with the first prototype of the ROIC, as well as to discuss the data acquisition process.
...
This article presents the experimentally characterized performance of a low noise and wideband sensor readout integrated circuit (ROIC). The ROIC is designed to detect small amounts of charge generated by a silicon p-i-n detector as a result of particle detection, with very high time resolution and limited power consumption. The architecture of the ROIC permits the analog components of the particle readout to be designed with a reduced bandwidth by implementing the so-called intersymbol interference (ISI) cancellation technique, which improves the noise performance, while reducing the deterministic ISI-induced errors associated with the narrowband circuit; hence, a low error rate (ER) can be maintained. The readout is designed to detect 160 aC charge portions delivered randomly by the detector at a maximum of 4 × 108 events/s with a small average ER while consuming 2.85 mW. Detailed information about the ROIC designed in 65-nm CMOS technology, and the simulated performance, are already reported in a previous publication. This article aims to present the challenges related to the design of the test setup and the obtained experimental results with the first prototype of the ROIC, as well as to discuss the data acquisition process.
Particle detection circuits are used for a wide range of applications from experimental physics to material testing and medical imaging. In the state-of-The-Art systems, the trend is to design low-noise and low-power readout front-end electronics with a low detection error rate and small silicon area occupation. This paper presents the design of a high time resolution, low-noise, and power-efficient charge sensitive amplifier (CSA) in 40 nm CMOS technology. For every charge pulse of the detector, the CSA generates voltage signals with a peak amplitude of 30.6 mV, a rise time of 2.35 ns, and an equivalent noise charge (ENC) of 44e- with 0.14 mW power consumption.
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Particle detection circuits are used for a wide range of applications from experimental physics to material testing and medical imaging. In the state-of-The-Art systems, the trend is to design low-noise and low-power readout front-end electronics with a low detection error rate and small silicon area occupation. This paper presents the design of a high time resolution, low-noise, and power-efficient charge sensitive amplifier (CSA) in 40 nm CMOS technology. For every charge pulse of the detector, the CSA generates voltage signals with a peak amplitude of 30.6 mV, a rise time of 2.35 ns, and an equivalent noise charge (ENC) of 44e- with 0.14 mW power consumption.
Particle detection circuits are used for a wide range of applications from experimental physics to material testing and medical imaging. State-of-the-art imaging systems, such as scanning electron microscopes (SEMs), demand the ability to detect small amounts of charge with small time-resolution and limited power consumption, creating an implementation dead-end for conventional readout topologies. In this paper, a particle detection readout based on an intersymbol interference cancellation scheme is introduced to address this issue. Evaluated in post-layout simulations, the proposed architecture can detect generated charges as small as 160 aC with 97.8% certainty. The readout can operate with event rates up to 400 MEvent/s while only consuming 2.85 mW of power.
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Particle detection circuits are used for a wide range of applications from experimental physics to material testing and medical imaging. State-of-the-art imaging systems, such as scanning electron microscopes (SEMs), demand the ability to detect small amounts of charge with small time-resolution and limited power consumption, creating an implementation dead-end for conventional readout topologies. In this paper, a particle detection readout based on an intersymbol interference cancellation scheme is introduced to address this issue. Evaluated in post-layout simulations, the proposed architecture can detect generated charges as small as 160 aC with 97.8% certainty. The readout can operate with event rates up to 400 MEvent/s while only consuming 2.85 mW of power.