State-of-the-art readout integrated circuits (ROICs) operating in particle-counting mode are gravitating toward high time resolution, low-noise, and low-power analog readout frontends to detect and register the arrival time of charge signals with a high accuracy. To achieve a time resolution of a few nanoseconds, an intermediate stage, known as a signal shaper block, is the preferred solution in the readout frontend, as it compensates for the inter-symbol interference-induced errors by realizing a band-pass transfer function. This paper presents the design methodology and experimental characterization of a state-of-the-art, high time resolution, low-offset, and power-efficient band-pass signal shaper block intended for fitting the voltage signals generated by a charge-sensitive amplifier (CSA) as a function of charge signals as small as 160 aC, into timeframes of 2.5 ns with 17 times offset attenuation while consuming 0.17 mW of power. Detailed information about the operation principle of this CSA, designed in TSMC 40 nm MS/RF CMOS technology, is reported in a previous publication.@en

This paper presents the design methodology, test setup and experimental qualification results of a high-speed low-power threshold comparator in 40 nm CMOS technology intended for the registry of particles landing on a PIN-detector surface in particle detector readout electronics. The operation of the designed comparator is experimentally qualified for ideal digital pulses and analog signals generated by the preceding stages in a targeted potential application.@en

Small charge detection is used for a wide range of applications: advanced industrial process control, experimental physics and space instruments, and material testing and medical imaging. These applications give rise to the development of a wide variety of charge-sensitive readout integrated circuits (ROICs). The trend in the state-of-the-art systems is to design low-noise and low-power readout electronics with a low detection error rate and small silicon area occupation, allowing the pixelization of the detector area. This paper presents the methodology and the test setup for the challenging experimental characterization of a state-of-the-art, high time-resolution, low-noise, power-efficient, charge-sensitive ROIC intended for counting single particles detected by a silicon PIN detector. The ROIC is designed to detect charge portions as small as 160 aC, with 0.14 mW power consumption. For every charge pulse of the detector, the ROIC generates voltage signals with a peak amplitude of 29.45 mV, a rise time of 2.56 ns, and an SNR above 20. Detailed information about the operation principle of this ROIC, designed in TSMC 40-nm MS/RF CMOS technology, is reported in a previous publication.@en

This article presents the experimentally characterized performance of a low noise and wideband sensor readout integrated circuit (ROIC). The ROIC is designed to detect small amounts of charge generated by a silicon p-i-n detector as a result of particle detection, with very high time resolution and limited power consumption. The architecture of the ROIC permits the analog components of the particle readout to be designed with a reduced bandwidth by implementing the so-called intersymbol interference (ISI) cancellation technique, which improves the noise performance, while reducing the deterministic ISI-induced errors associated with the narrowband circuit; hence, a low error rate (ER) can be maintained. The readout is designed to detect 160 aC charge portions delivered randomly by the detector at a maximum of 4 × 108 events/s with a small average ER while consuming 2.85 mW. Detailed information about the ROIC designed in 65-nm CMOS technology, and the simulated performance, are already reported in a previous publication. This article aims to present the challenges related to the design of the test setup and the obtained experimental results with the first prototype of the ROIC, as well as to discuss the data acquisition process.

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Particle detection circuits are used for a wide range of applications from experimental physics to material testing and medical imaging. In the state-of-The-Art systems, the trend is to design low-noise and low-power readout front-end electronics with a low detection error rate and small silicon area occupation. This paper presents the design of a high time resolution, low-noise, and power-efficient charge sensitive amplifier (CSA) in 40 nm CMOS technology. For every charge pulse of the detector, the CSA generates voltage signals with a peak amplitude of 30.6 mV, a rise time of 2.35 ns, and an equivalent noise charge (ENC) of 44e- with 0.14 mW power consumption.

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Particle detection circuits are used for a wide range of applications from experimental physics to material testing and medical imaging. State-of-the-art imaging systems, such as scanning electron microscopes (SEMs), demand the ability to detect small amounts of charge with small time-resolution and limited power consumption, creating an implementation dead-end for conventional readout topologies. In this paper, a particle detection readout based on an intersymbol interference cancellation scheme is introduced to address this issue. Evaluated in post-layout simulations, the proposed architecture can detect generated charges as small as 160 aC with 97.8% certainty. The readout can operate with event rates up to 400 MEvent/s while only consuming 2.85 mW of power.@en

Particle detection circuits are used for a wide range of applications from experimental physics to material testing and medical imaging. State-of-the-art imaging systems, such as scanning electron microscopes (SEMs), demand the ability to detect small amounts of charge with small time-resolution and limited power consumption, creating an implementation dead-end for conventional readout topologies. In this paper, a particle detection readout based on an intersymbol interference cancellation scheme is introduced to address this issue. Evaluated in post-layout simulations, the proposed architecture can detect generated charges as small as 160 aC with 97.8% certainty. The readout can operate with event rates up to 400 MEvent/s while only consuming 2.85 mW of power.@en