Design and Qualification of a High-Speed Low-Power Comparator in 40 nm CMOS Technology

Mohammad Zaki, A.R.; Du, Yutong; Nihtianova, S.

doi:10.1109/ET59121.2023.10278935

Design and Qualification of a High-Speed Low-Power Comparator in 40 nm CMOS Technology

Conference paper (2023)

Authors

A.R. Mohammad Zaki Electronic Instrumentation -

Yutong Du Student

S. Nihtianova Electronic Instrumentation -

Research Group

Electronic Instrumentation () (TU Delft)

DOI: https://doi.org/10.1109/ET59121.2023.10278935

Low-power Temperature sensor High-speed Readout interface Voltage comparator

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Published Date

2023

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronic Instrumentation

Abstract

This paper presents the design methodology, test setup and experimental qualification results of a high-speed low-power threshold comparator in 40 nm CMOS technology intended for the registry of particles landing on a PIN-detector surface in particle detector readout electronics. The operation of the designed comparator is experimentally qualified for ideal digital pulses and analog signals generated by the preceding stages in a targeted potential application.

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