Design and Qualification of a High-Speed Low-Power Comparator in 40 nm CMOS Technology
Alireza Mohammad Zaki (TU Delft - Electronic Instrumentation)
Yutong Du (Student TU Delft)
Stoyan Nihtianova (TU Delft - Electronic Instrumentation)
More Info
expand_more
Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.
Abstract
This paper presents the design methodology, test setup and experimental qualification results of a high-speed low-power threshold comparator in 40 nm CMOS technology intended for the registry of particles landing on a PIN-detector surface in particle detector readout electronics. The operation of the designed comparator is experimentally qualified for ideal digital pulses and analog signals generated by the preceding stages in a targeted potential application.