State-of-the-art readout integrated circuits (ROICs) operating in particle-counting mode are tending toward high time resolution in the nanosecond range, low-noise for accurate detection of lower-energy particles, and low-power consumption allowing the use of multiple channels on a single die. In previous reports we have presented a particle counting ROIC comprising: a charge-sensitive amplifier (CSA), an active shaping filter, and a discriminator. The use of an active shaping filter provides additional gain for the signal, which relaxes the requirements for the discriminator and makes it more power-efficient. At the same time, the active shaping filter itself consumes a considerable amount of power to operate properly. In this paper we present an alternative solution, based on the same architecture, in which the active shaping filter is replaced by a passive high-pass RC filter with no static power consumption. The price to pay is increased power consumption of a more advanced discriminator with periodic offset compensation. Nevertheless, we report a comparable performance of the two solutions with a 32% overall power reduction with the passive RC filter. The design is made for TSMC 40nm MS/RF CMOS technology.

This paper presents the design methodology, test setup and experimental qualification results of a high-speed low-power threshold comparator in 40 nm CMOS technology intended for the registry of particles landing on a PIN-detector surface in particle detector readout electronics. The operation of the designed comparator is experimentally qualified for ideal digital pulses and analog signals generated by the preceding stages in a targeted potential application.