A High Input Impedance Readout Integrated Circuit based on Continuous-Time Sigma-Delta Modulator with FIR DAC Feedback

Master Thesis (2022)
Author(s)

J. YU (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Contributor(s)

Stoyan Nihtianova – Mentor (TU Delft - Electronic Instrumentation)

Hui Jiang – Mentor (Silicon Integrated B.V.)

C. Gao – Graduation committee member (TU Delft - Electronics)

Faculty
Electrical Engineering, Mathematics and Computer Science
Copyright
© 2022 Jinqian YU
More Info
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Publication Year
2022
Language
English
Copyright
© 2022 Jinqian YU
Graduation Date
28-09-2022
Awarding Institution
Delft University of Technology
Programme
['Electrical Engineering | Microelectronics']
Sponsors
Silicon Integrated B.V.
Faculty
Electrical Engineering, Mathematics and Computer Science
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Abstract

This thesis focuses on the design of a high input impedance sensor readout system based on a continuous-time sigma-delta modulator with finite-impulse-response digital-to-analog converter feedback.

Both the system-level and circuit-level design techniques of this system are investigated. The concept and design methods of finite-impulse-response digital-to-analog converters are introduced. The first integrator with source degeneration resistors and an input Gm-boosting cell is designed to achieve high input impedance and linearity. Both simulation and post-layout simulation results confirm the expected effective number of bits of 15 bits in the readout performance. The design is fabricated in a standard 180nm CMOS technology.

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