SPAIC: A sub-μW/Channel, 16-Channel General-Purpose Event-Based Analog Front-End with Dual-Mode Encoders

Conference paper (2023)

Authors

Shyam Narayanan University of Zürich, ETH Zürich
Matteo Cartiglia ETH Zürich, University of Zürich
Arianna Rubino University of Zürich, ETH Zürich
Charles Lego University of Zürich, ETH Zürich
C. Frenkel Electronic Instrumentation - EEMCS
Giacomo Indiveri ETH Zürich, University of Zürich
Research Group
Electronic Instrumentation (EEMCS) (TU Delft)
Copyright: © 2023 Shyam Narayanan, Matteo Cartiglia, Arianna Rubino, Charles Lego, C. Frenkel, Giacomo Indiveri
DOI
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https://doi.org/10.1109/BioCAS58349.2023.10388815
Neuromorphic Spiking Neural Network (SNN) Analog Front-End (AFE) Encoder
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Published Date

2023

Language

English

Reuse Rights

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronic Instrumentation

Abstract

Low-power event-based analog front-ends (AFE) are a crucial component required to build efficient end-to-end neuromorphic processing systems for edge computing. Although several neuromorphic chips have been developed for implementing spiking neural networks (SNNs) and solving a wide range of sensory processing tasks, there are only a few general-purpose analog front-end devices that can be used to convert analog sensory signals into spikes and interfaced to neuromorphic processors. In this work, we present a novel, highly configurable analog front-end chip, denoted as "SPAIC" (signal-to-spike converter for analog AI computation), that offers a general-purpose dual-mode analog signal-to-spike encoding with delta modulation and pulse frequency modulation, with tunable frequency bands. The ASIC is designed in a 180nm process. It supports and encodes a wide variety of signals spanning 4 orders of magnitude in frequency, and provides an event-based output that is compatible with existing neuromorphic processors. We validated the ASIC for its functions and present initial silicon measurement results characterizing the basic building blocks of the chip.