Continual learning (CL) enables models to learn sequentially from non-stationary data without catastrophic forgetting, which is critical for real-world applications such as robotics and embedded systems. However, implementing CL on edge devices remains challenging due to limited memory and computational resources. Replay-based methods, while effective for CL, impose large memory overheads for storing replay samples.

This thesis proposes a compressed latent replay (CLR) framework to enable memory-efficient on-chip CL for both deep neural networks (DNNs) and spiking neural networks (SNNs). The algorithmic design integrates spatial compression via autoencoders to reduce latent dimensionality, temporal compression via spike counting and binning to exploit SNN sparsity, and their two-dimensional combination for further memory reduction. Experiments on MNIST and SHD validate the software framework. On MNIST, two-dimensional compression (TW=20, dim_latent=20) preserves accuracy (89.0% vs 88.0% uncompressed) while reducing replay storage from 245 KB to 62.81 KB, corresponding to 25.6% of the baseline. When the number of replay samples increases, the advantage becomes more pronounced; with 256 samples per class the footprint is 64.37 KB versus 490 KB, corresponding to 13.1% of the uncompressed baseline. On SHD, temporal spike counting maintains strong accuracy under compression and outperforms binning.

To validate system-level feasibility, two FPGA accelerators were implemented on the AMD Kria KV260 with DMA over AXI and AXI-Stream: a Time Decoder and a sparse FC accelerator that supports hardware forward propagation with software backpropagation. The Time Decoder shortens the decoding of 128 × 5 temporally compressed spike sequences from 17.4 s on the Cortex-A53 to 1.2 s (~14.5×). The FC accelerator reduces per-FC computation time on a 784 × 64 layer with batch 128 from 2.240 ms (CPU) to 1.108 ms (P=16) and 0.323 ms (P=64), yielding up to 6.94× speedup. End-to-end latency remains higher due to CPU-side preprocessing and data movement. Resource usage meets KV260 limits, with logic and DSP utilization remaining moderate, while BRAM is the dominant constraint at higher parallelism.

Overall, this work shows that CLR combined with FPGA acceleration and hardware forward with software backpropagation is a practical and scalable route to on-device CL in edge AI systems. Potential extensions include quantized autoencoders, sparsity-aware BRAM allocation for edge-realistic temporal datasets, pipelined or PL side preprocessing to reduce end-to-end latency to strengthen deployment feasibility.

This study explores the integration of asynchronous event-driven circuitry with photon-counting technology to enhance detection performance in modern computed tomography (CT) systems. Asynchronous circuits are wellsuited for event-driven applications, including photon-counting imaging. However, conventional architectures such as the threshold subtraction (TS) and direct binning (DB) schemes have not been implemented at the circuit level, and their performance is limited by challenges such as pulse pile-up and charge crosstalk.

To address these limitations, we propose a novel pileup-specific (PS) system that mitigates pile-up effects by extracting both the onset and peak information of pulse events. Furthermore, the multi-energy inter-pixel coincidence counters (MEICC) system, a state-of-the-art solution for charge crosstalk, is shown to be highly compatible with our PS design. Using the open-source asynchronous circuit toolkit (ACT), we successfully implemented the TS, PS, and MEICC systems as asynchronous digital circuits. Transistor-level simulations demonstrate that the proposed PS system significantly improves counting accuracy under pile-up conditions compared to the conventional TS approach, with only minor trade-offs in speed and area. Additionally, benchmark comparisons with synchronous designs indicate that the asynchronous implementations offer superior power efficiency and operational robustness in photon-counting applications. These results highlight the potential of asynchronous event-driven circuits to enable the next generation of CT imaging systems with improved accuracy, energy efficiency, and reliability.

The rapid growth in the energy consumption of artificial intelligence (AI) models has made low-power, high-efficiency, brain-inspired computing hardware a central research focus. Hierarchical temporal memory (HTM) offers robustness and energy efficiency via its spatial pooler (SP) and the use of sparse distributed representations (SDRs), but its temporal memory (TM) is highly sensitive to input perturbations. Moreover, most existing hardware efforts target isolated modules rather than a complete, efficient inference loop. To address these issues, we employ the HTM SP as a sparse encoder and replace TM with deep neural networks, proposing a dual-path SP+FCNN/RNN framework. On sequential MNIST, this scheme achieves 96.5% classification accuracy and markedly improves generalization.

Targeting the three computational bottlenecks revealed in the algorithmic analysis: SP overlap dot products, k-WTA sorting, and neural network multiply-accumulate operations, this work designs a 25-lane parallel binary dot-product accelerator (MAC-SP), a hierarchical min-heap sorting accelerator (Heap-Sort), and a 16 × 16 systolic-array accelerator (MAC-NN). All three accelerators are integrated, with a unified (memory-mapped input/output) MMIO interface, into the open-source CROC SoC built around an Ibex core. Logic synthesis in a 40 nm process shows that the complete SoC occupies only 0.112 mm2, consumes 1.078 mW, and achieves a maximum clock frequency of 400 MHz. Relative to the pure software baseline, the three core operations achieve speedups of 28.7×, 23.5×, and 38.1×, respectively. End-to-end inference for a single MNIST image drops from 3.78 × 107 to 1.43 × 106 clock cycles, for an overall 26.4× speedup.

This thesis asks whether spiking neural networks (SNNs) and neuromorphic computing constitute a promising alternative to present-day artificial neural networks (ANNs) for autonomous space missions. Focusing on a resource- and power-constrained 1U CubeSat transiting the Van Allen radiation belts, TIENOS is a toolchain that injects radiation-inspired perturbations into trained models and records the layer-specific reactions.

The framework systematically emulates dominant soft-error mechanisms by applying (i) bit-flip faults representative of single-event upsets, (ii) additive Gaussian noise as a proxy for thermal/analog variability, and (iii) dropout-style masking to approximate transient loss or zeroing of activations. Using MNIST (frame-based) and N-MNIST (event-based) benchmarks, we compare LeNet-5–style convolutional neural networks and size-matched multilayer perceptrons with their spiking counterparts to establish an ideal software training baseline. The tool produces per-layer vulnerability profiles and robustness heatmaps across a broad range of perturbation rates, quantifies activity sparsity in SNNs, and can be used to evaluate noise-aware retraining to improve robustness without any overhead, with a path towards on-chip protections such as selective redundancy (such as triple-modular redundancy for neuron parameters), ECC and scrubbing.

Results show that fragility concentrates in a limited subset of layers depending on the fault mechanism, enabling targeted hardening with modest cost. It also indicates that noise-aware retraining improves tolerance without prohibitive accuracy loss and that SNN sparsity yields favourable energy–robustness trade-offs for bursty, event-driven sensing typical of small spacecraft. In this study, the noise-aware learned weights used for inference by the two-tinyODIN setup deliver a 15% higher accuracy for up to 2% of bit-flips in the system. Hybrid ANN–SNN pipelines could further enlarge this envelope by deploying spiking computation where sparsity is highest while retaining dense processing elsewhere, acknowledging that the scalability and baseline power of current neuromorphic platforms remain practical constraints. Overall, the methodology translates environmental assumptions for a 1U CubeSat in the Van Allen belts into actionable, layer-level design rules, providing a principled basis for space-grade, energy-efficient digital SNN accelerators and an open, extensible tool to localise and mitigate radiation-induced vulnerabilities.

Spiking Neural Networks (SNNs), inspired by biological neural systems, operate in an event-driven manner with sparse activity. As a result, neuromorphic hardware implementing SNNs holds strong potential for ultra-low-power processing, making it ideal for edge-AI applications. However, conventional digital hardware accelerators rely on an always-on global clock, where the clock tree alone can account for 30–50% of the total power consumption. To better exploit the sparse activity of SNNs, this thesis investigates event-driven clocking schemes for digital neuromorphic circuits. A complete neuromorphic system is built using a software-hardware co-design methodology, serving as a platform for experimentation. Fine-grained clock gating is first applied, enabling event-driven operation from the layer level down to neuron-group granularity. As an alternative, local clock generators are implemented to replace traditional gated clocks. Logic synthesis and place-and-route are performed to evaluate power consumption and clock tree efficiency. Results demonstrate that these event-driven approaches, particularly local clocking, significantly reduce power and clock tree overhead while maintaining high performance. Our design achieves 97.6% classification accuracy on MNIST application with 189 μW power consumption and energy of 329 nJ per inference, highlighting its promise for energy-efficient neuromorphic processors in always-on edge-AI scenarios.

Tailless flapping-wing drones mimic the flight mechanics of insects and offer unique advantages in agility and maneuverability compared to rotor-based drones. Yet, their limited onboard computational resources and non-linear flight dynamics complicate active attitude control. Neural network-based controllers have shown promising control performance for this task but they exceed a flapping-wing drone's onboard computational budget. To this end, the Sparse Identification of Nonlinear Dynamics (SINDy) algorithm offers a promising solution by distilling a neural network-based controller into a simplified mathematical expression. This expression is better suited for mapping onto an FPGA which provides the power efficiency essential for an energy-constrained drone. The current work presents an automated workflow to translate the simplified controller into an HDL description, maximizing DSP block usage for power and resource efficiency. Demonstration of this workflow on the pendulum simulation as a proof-of-concept has shown its efficacy. The included optimization techniques have resulted, on average, in a 40% reduction of DSP block usage, without compromising controller performance. This scalable, platform-agnostic workflow streamlines the design of a controller's hardware implementation and allows its future application to a flapping-wing drone.

Flapping-wing micro air vehicles (FWMAVs) present a significant control challenge due to their complex nonlinear dynamics and severe hardware constraints, which preclude the use of computationally intensive controllers. This thesis addresses this challenge by developing and validating a pipeline to convert a high-performance neural network policy, trained via Reinforcement Learning (RL), into a sparse, hardware-efficient symbolic controller using the Sparse Identification of Nonlinear Dynamics (SINDy) framework. The primary contribution of this work is the introduction and evaluation of novel, hardwareaware optimizations within the SINDy distillation process. Specifically, we introduce Sparse Bit Quantization (SBQ), a new quantization scheme that represents coefficients as combinations of powers of two to enable efficient implementation using bit-shift operations on an FPGA. We systematically analyze the impact of applying SBQ both post-training and during the optimization loop (Quantization-Aware Training), and further explore the use of a custom, hardware-efficient function library designed to map directly to DSP block structures. The complete pipeline was validated on the ‘Pendulum-v1‘ benchmark. Our results demonstrate that while standard SINDy can accurately approximate the RL teacher policy, our hardware-oriented function library, struggles to capture the full complexity of the control task. This highlights a key trade-off between hardware-efficiency and model expressiveness. This work serves as a successful proof-of-concept and contributes novel techniques essential for deploying modern control algorithms on resource-constrained robotic systems.

Traditional computing approaches based on the von Neumann architecture consist of physically separate storage and computation units. This requires the data to be moved back and forth between the storage and computation units, resulting in increased latency and energy costs known as the memory-wall bottleneck. To address this issue, in-memory computing has emerged as a possible solution wherein computation is performed directly inside the memory units, similar to the working of the human brain. Memristor devices arranged in a cross-bar array formation are promising candidates for such in-memory accelerators as they enable direct processing of data within memory. Despite the promises shown by memristors, they still suffer from non-idealities which hinder their application as neural network accelerators such as asymmetric conductance update, device-to-device variations, and temporal drift. While it is possible to optimize the parameters of the neural network in the cloud to reduce the impact of these non-idealities, the drawback of this approach is that the trained model is unable to adapt to new tasks. This thesis proposes using a bi-level optimization scheme such as meta-learning to overcome the effect of memristor non-idealities. Meta-learning (or learning-to-learn) is a field of machine learning that allows neural networks to learn from multiple tasks and use that experience to improve performance on future tasks. Using the model agnostic meta-learning (MAML) algorithm, it is possible to train neural networks such that the impact of memristor non-idealities is reduced. Incorporating memristor dynamics in a traditional machine learning setup resulted in a classification accuracy of up to 59.20% on the Omniglot dataset with a 5-layer convolutional neural network, a sharp decrease from the baseline accuracy of 97.5%. This thesis demonstrates that using MAML on the Omniglot dataset for the five-way one-shot learning task results in neural networks achieving a classification accuracy of up to 97.5% when considering asymmetric conductance updates of memristors, which is equivalent to the accuracy obtained when training the neural network using ideal memristor dynamics. Furthermore, when taking into account device-to-device variations, accuracy values of up to 87.5% are obtained. Finally, when accounting for temporal drift, accuracy values greater than 70% were maintained for up to 11 inference steps using MAML when considering the ratio of learning steps to the temporal drift to be 1:100.

Radar-based sensors are used to perceive their environment and objects of interest in a contactless manner and with robust performance in all weather and light conditions. One of the main drawbacks is the energy needed for the processing of radar data in order to extract its valuable information. Spiking neural networks are an emerging type of neural networks that aim to reduce the energy footprint of their computations while maintaining acceptable performance. To do so, the data is encoded through time in binary spikes to help leverage the low cost of additions. This is in stark opposition to the much higher cost of multiplications that are highly present in conventional artificial neural networks. The drawback of this energy gain is that the rate encoding adds an extra time dimension, hence increasing the latency between the acquisition of the radar data and the recognition of the corresponding gesture class.
More specifically, this work uses an air-marshalling dataset from the literature to exemplify a gesture recognition problem. The first step is to replicate the well-known radar processing pipeline, and classification approach based on conventional neural networks to reach high classification accuracies. A validation accuracy of 98.5% and a test accuracy of 59.8% are reached on the full dataset (11 classes) and 86.7% on their 5 best classes (test set), which is about the same performance reported in the original dataset baseline.
The following steps propose an adaptation of this non-spiking pipeline to its spiking equivalent by optimising the trade-off between the model’s latency, its memory requirements and its accuracy. This work also develops a strategy to tune spiking networks’ thresholds to make the process of developing a spiking equivalent more efficient. For example, the spiking network can reach 94.1% validation accuracy using 100 encoding steps and only 4.7% of the initial memory requirements, and reach 46.8% on the test set. However, this trade-off can be shifted towards lower latency, lower memory, or higher accuracy according to the desired requirements.

State-space models (SSMs) combine attention-like parallelization with RNN-like inference efficiency, using internal states with linear update and output functions, similar to RNNs but without non-linearities in the update function. Linear Recurrent Units (LRUs), a type of SSM, are well-suited to keyword spotting due to their ability to handle long-range dependencies. However, hardware acceleration for LRUs remains unexplored and presents challenges due to high hardware cost components such as the GELU, LayerNorm and complex multiplication. This work modifies the LRU model architecture to enable a more efficient hardware implementation and designs an accelerator tailored to the modified architecture. We propose the GRELU, a new activation function well-suited to inference on hardware. The modified model architecture achieved an accuracy of 95.5% on the Google Speech Commands dataset. The accelerator's vector unit supports complex operations and reductions, with respective overheads of only 19.1% and 27.2% over basic operations. Our results demonstrate the proposed hardware accelerator's efficiency and effectiveness at keyword spotting applications.

This thesis serves to finalise the bachelor graduation project on the topic of self-supervised federated learning, specifically the on-chip implementation of the algorithms. The goal of the project is to implement a self-supervised learning setup in a decentralised approach using Field-Programmable Gate Arrays (FPGAs) for the processing of data. In this thesis, we endeavour to illustrate the possibility of employing FPGAs to move the fairly compute-intensive self-supervised learning algorithms to the edge. We have developed a number of modules that can accelerate key algorithmic blocks that underlie the major bottlenecks of the classical application of the algorithms and showcase prospective results, which are extensively discussed afterwards to pave a clear path towards truly autonomous and efficient edge-intelligence.

This report serves to finalize the bachelor graduation project on the topic of self-supervised federated learning, specifically the implementation of the algorithms in Python. The goal of the project is to implement a self-supervised learning setup in a decentralized approach using Field-Programmable Gate Arrays (FPGAs) for the processing of data. This serves as a proof of concept that decentralized machine learning on unlabeled data using FPGAs is possible. Multiple algorithms based on the literature were considered to allow for a low-profile learning setup, with simplifications done to be able to reduce the compute required. The results are promising: scaled-down models that can run on an FPGA show that self-supervised learning functions as expected from the theory. By decentralizing the computations increases in performance are possible in favorable conditions. The authors hope that the concept of self-supervised federated learning can be employed to FPGAs on a larger scale to help in the processing of the abundant yet underutilized unlabeled data present at the edges of information networks.

Olfactory learning in Drosophila larvae exemplifies efficient neural processing in a small-scale network with minimal power consumption. This system enables larvae to anticipate important outcomes based on new and familiar odor stimuli, a process crucial for survival and adaptation. Central to this learning mechanism is the olfactory pathway model, which embodies the principles of synaptic plasticity and associative learning through prediction error coding mediated by specific neuromodulating neurons in the mushroom body, like dopaminergic neurons. There is a pressing need to develop novel computational frameworks that capture the spatio-temporal processes while remaining compatible with the constraints of small-scale neural networks. These frameworks should draw inspiration from the biophysical properties of neurons within the olfactory pathway model, enabling accurate emulation of neural dynamics and efficient learning processes using spiking neural networks. This thesis proposes a framework based on a phenomenological conductance-based leaky integrate-and-fire (COBALIF) neuron model, inspired by the olfactory pathway model of Drosophila larvae. By first prototyping the spiking neural network in Intel's Lava Python-based framework, we validated the design on a neuron and system level for a neuromorphic hardware implementation. This was the foundation of a programmable, neuromorphic FPGA architecture capable of adaptive optimization, employed on a Zynq 7000 SoC FPGA. By implementing this architecture in a single-precision floating-point format, we model the real-time neural dynamics of the COBALIF neuron in one-tenth of a millisecond precision. Moreover, our FPGA implementation serves as a feasible prototype for deploying such biologically inspired neurons and their spatio-temporal dependencies in digital design, paving the way for scaling up to small-scale networks.

Nowadays, to reduce the dependence of devices on cloud servers, machine learning workloads are required to process data on the edge. Furthermore, to improve adaptability to uncontrolled environments, there is a growing need for on-chip learning. Limitations in power and area for edge devices have increased interest in low-cost neural network learning algorithms. However, as edge platforms are increasingly multi-core, new techniques are required to deploy learning algorithms on multi-core designs.
In this report, the performance of a low-cost multi-core on-chip learning platform with the local error learning (LEL) algorithm is evaluated. First, we reviewed state-of-art learning algorithms designed to solve the challenges of efficient neural network learning. We analyze these algorithms from the point of view of performance, hardware overhead, scalability, and the possibility of multi-core implementation. We propose a spatio-temporal learning framework for the combined use of LEL and e-prop. As a first proof of concept, we aim first at demonstrating multi-core LEL learning for image classification. Next, we constructed a software model suitable for multi-core on-chip driven by hardware requirements. With the software model, we then implemented the corresponding hardware and deployed it on a system-on-chip field programmable gate array (SoC FPGA) board to evaluate the performance. Results based on the CIFAR-10 image classification dataset show that the hardware design can fully reproduce the software runtime results. With a classification accuracy of 59.57\% after batch-size-1 on-chip learning, our design forms a stepping stone for the development of low-cost multi-core hardware that can adapt online to its environment.

Event-based cameras promise new opportunities for smart vision systems deployed at the edge. Contrary to their conventional frame-based counterparts, event-based cameras generate temporal light intensity changes as events on a per-pixel basis, enabling ultra-low latency with microsecond-scale temporal resolution, low power consumption at milliwatts level, and sparse information encoding where only dynamic objects trigger events, effectively excluding static background data. However, mainstream computer vision algorithms based on convolutional neural networks (CNNs) hardly exploit these advantages of event-based cameras. Recently, event graph neural networks (event-GNNs) have been proposed as the backbone for novel event-based vision algorithms. By treating events as graph data, GNNs are able to process events while preserving their spatiotemporal information and sparse characteristics. Further studies also revealed an event-driven computation workflow that translates an event stream into a dynamic, evolving graph, outlining a path toward low-latency event-based vision. Despite these promises, event-GNNs are still calling for dedicated hardware accelerators toward integrated solutions with real-time prediction latency and low power consumption for real-world edge intelligence.

In this thesis, for the first time, we proposed an event-driven GNN accelerator for low-power, high-speed edge vision. Through hardware-algorithm co-design, an event-driven GNN model is adopted for deployment on an edge FPGA platform without prediction accuracy loss. We also pointed out two novel optimizations, edge-free storage and layer-parallel computation, to further decrease memory footprints and processing latency. The proposed accelerator is implemented on the Xilinx KV260 System-On-Module (SOM) platform containing an UltraScale+ MPSoC FPGA, and benchmarked on-board. Targeting a car recognition task based on the NCars dataset, our accelerator achieves a prediction accuracy of 87.8%. Meanwhile, operating with a 6.86W board-level system power, the accelerator reaches an average 16μs prediction latency per event and runs 9.2× faster than its software counterpart running on an NVIDIA RTX A6000 GPU platform. Therefore, our event-driven GNN accelerator efficiently allows for both real-time and microsecond-resolution event-based vision at the edge.

The growing interest in edge computing is driving the demand for more efficient deep learning models that fit into resource-constrained edge devices like Internet-of-Things (IoT) sensors. The challenging limitations of these devices in terms of size and power has given rise to the field of tinyML, focusing on enabling low-cost machine learning on edge devices. Up until recently, the work in this space was primarily focused on static inference scenarios. However, a prominent issue with this is that models cannot adapt post-deployment, leading to robustness issues with shifting data distributions or the introduction of new features in the data. However, at the edge, full on-device retraining, or communicating all new data to a central server, is infeasible: this necessitates the development of data-efficient learning algorithms to adapt locally and autonomously from streaming data. This challenge at the intersection of edge computing and data-efficient learning is currently an open challenge.
In this thesis, we propose to solve this challenge with meta-learning. To clarify in which way the application of meta-learning is the most suitable for edge hardware, for the first time, a principled approach for meta-learning at the edge is outlined and investigated in three parts.
The first part of this thesis details the selection of a suitable neural network architecture for few-shot learning over sequential data. By not being fixated on one architecture from the start, it is possible to explore different approaches to learning over sequences of temporal data, leading to the identification of the most effective architecture for generalizing from limited temporal examples. The quantitatively evaluated architectures are a recurrent neural network (RNN), a gated recurrent unit (GRU), a long-short-term memory (LSTM) and a temporal convolutional network (TCN). We show that TCNs outperform all architectures, while GRUs and LSTMs have a lower activation memory requirement. However, the latter require a linearly increasing number of multiplications with input sequence length, while it scales logarithmically for TCNs. Our results show that TCNs therefore provide the most favorable trade-off for low-cost temporal feature extraction at the edge.
The second part of the thesis focuses on the algorithmic developments of the few-shot learning setup. Building on recent results from machine learning research, we highlight how meta-learning techniques primarily rely on learning high-quality features that generalize well. Taking into account hardware-driven considerations such as memory and compute overheads and through detailed quantitative analyses, we demonstrate that the best performance-cost trade-off is reached with a simple supervised pre-training scheme, where on-chip learning is performed by comparing the outputs of a TCN-based feature extractor with Manhattan distance. We also analyze the impact of quantization on this trade-off and, accordingly, we select a scheme with 4-bit logarithmic weights and 4-bit unsigned activations...

Spiking neural networks (SNNs), which are regarded as the third generation of neural networks, have attracted significant attention due to their promising applications in various scenarios. Based on SNNs, neuromorphic coprocessors, designed to emulate the structure and functionality of biological brains, hold the potential to revolutionize computing. However, these coprocessors encounter challenges related to adaptability and flexibility in various application environments once they are manufactured. To tackle this challenge, our project introduces a neuromorphic System-on-Chip (SoC), which seamlessly integrates a RISC-V CPU with an SNN coprocessor, utilizing sparse time-to-first-spike encoding (TTFS). The primary goal of this SoC is to facilitate the complete reconfigurability of the SNN coprocessor with the RISC-V CPU. By leveraging this neuromorphic SoC and successfully simulating the novel loop learning work model to achieve an accuracy of 92.2\% on the MNIST dataset, we demonstrate its capability to adapt the SNN coprocessor for various application scenarios, such as text recognition and face detection.

With the introduction of event-based cameras, such as the dynamic vision sensor (DVS), new opportunities have arisen for low-latency real-time visual data processing. Unlike traditional frame-based cameras that capture entire frames at fixed intervals, each pixel in an event-based camera operates asynchronously, generating an event whenever its brightness change exceeds a certain threshold. Although DVS sensors inherently surpass traditional frame-based cameras in capturing transient, high-speed phenomena, their performance bottleneck is usually located in their address event representation (AER) readout interfaces. The commonly used row-scanning synchronous AER, which encodes events in a full row at once, offers high throughput. However, this approach also introduces inherent delays that limit its use in applications requiring high temporal resolution. Conversely, while AER schemes based on asynchronous digital circuits surpass synchronous schemes in temporal resolution, their event-by-event transmission approach limits their overall throughput.

This work proposes a novel high-speed asynchronous AER interface, leveraging spatiotemporal correlations in DVS event-based data, to optimize the tradeoff between temporal resolution and throughput. Supported by the recently proposed open-source asynchronous design toolkit (ACT) flow for asynchronous digital circuits, we propose an address fuser to be integrated into the hierarchical token ring (HTR) AER scheme. This address fuser creates a spatiotemporal window to exploit the inherent spatiotemporal correlations in DVS data. After verification at both switch- and transistor-level simulations, we benchmarked our design against the conventional HTR AER scheme using a representative set of input scenarios. Our design achieved 196% of the throughput for multi-event transmissions when all pixels were activated simultaneously, at the expense of an acceptable 18% latency increase for single-event transmissions with a 10-ns temporal window.

The creation of effective computational models that function within the power limitations of edge de- vices is an important research problem in the field of Artificial Intelligence (AI). While cutting-edge deep learning algorithms show promising results, they frequently need computing resources that are many orders of magnitude more than the available power and memory budgets for these devices. During the thesis, two unique learning algorithms (backpropagation and forward-forward) were developed and compared using the Teensy 4.1, a low-cost microcontroller board. This work seeks to bridge the gap between the necessary computing efficiency and the hardware’s restricted resources.

By creating and analyzing these algorithms, with the Fashion MNIST dataset as a validation set, this thesis creates a baseline for AI efficiency on microcontrollers, with performance targets set at a mini- mum of 80% test accuracy. The microcontroller software, implemented in C++, is limited to using less than 512 kB RAM for all online training methods. In addition, the potential of transfer learning was also explored.

Key performance parameters, including memory utilization, training and inference times, and accu- racy, were analyzed in a comparative study of the backpropagation and forward-forward algorithms. For each learning algorithm, several configurations were explored (such as topologies, and optimizers) to determine the most effective and efficient way for AI implementation on low-cost hardware. The key conclusions of this study reveal that backpropagation demonstrates superior performance in terms of both accuracy and computational efficiency. However, it requires more memory for storing variables, which may be a constraint in on-edge environments. Conversely, the forward-forward algorithm, while achieving lower accuracy, is more memory-efficient, making it a potential choice for less complex tasks or systems with severe RAM limitations.

The application of transfer learning showed potential to accelerate the learning process and to improve the final accuracy, hinting at an effective strategy for deploying advanced AI models on resource-limited edge devices.