This thesis serves to finalise the bachelor graduation project on the topic of self-supervised federated learning, specifically the on-chip implementation of the algorithms. The goal of the project is to implement a self-supervised learning setup in a decentralised approach using Field-Programmable Gate Arrays (FPGAs) for the processing of data. In this thesis, we endeavour to illustrate the possibility of employing FPGAs to move the fairly compute-intensive self-supervised learning algorithms to the edge. We have developed a number of modules that can accelerate key algorithmic blocks that underlie the major bottlenecks of the classical application of the algorithms and showcase prospective results, which are extensively discussed afterwards to pave a clear path towards truly autonomous and efficient edge-intelligence.