Design of Event-driven Local Clock Circuits for Ultra-low-power Neuromorphic Processors

Abstract

Spiking Neural Networks (SNNs), inspired by biological neural systems, operate in an event-driven manner with sparse activity. As a result, neuromorphic hardware implementing SNNs holds strong potential for ultra-low-power processing, making it ideal for edge-AI applications. However, conventional digital hardware accelerators rely on an always-on global clock, where the clock tree alone can account for 30–50% of the total power consumption. To better exploit the sparse activity of SNNs, this thesis investigates event-driven clocking schemes for digital neuromorphic circuits. A complete neuromorphic system is built using a software-hardware co-design methodology, serving as a platform for experimentation. Fine-grained clock gating is first applied, enabling event-driven operation from the layer level down to neuron-group granularity. As an alternative, local clock generators are implemented to replace traditional gated clocks. Logic synthesis and place-and-route are performed to evaluate power consumption and clock tree efficiency. Results demonstrate that these event-driven approaches, particularly local clocking, significantly reduce power and clock tree overhead while maintaining high performance. Our design achieves 97.6% classification accuracy on MNIST application with 189 μW power consumption and energy of 329 nJ per inference, highlighting its promise for energy-efficient neuromorphic processors in always-on edge-AI scenarios.