This article describes a PNP-based temperature sensor that achieves both high energy efficiency and accuracy. Two resistors convert the CTAT and PTAT voltages generated by a PNP-based front-end into two currents whose ratio is then digitized by a continuous-time (CT) Δ Σ -modulator. Chopping and dynamic-element-matching (DEM) are used to mitigate the effects of component mismatch and 1/f noise, while the spread in V _BE and in the ratio of the two resistors is digitally trimmed at room temperature (RT). Fabricated in a 0.18μ m CMOS process, the sensor occupies 0.12 mm ², and draws 9.5μ A from a supply voltage ranging from 1.7 to 2.2 V. Measurements on 40 samples from one batch show that it achieves an inaccuracy of ± 0.1° C (3σ) from -55° C to 125° C, and a commensurate supply sensitivity of only 0.01° C/V. Furthermore, it achieves high energy efficiency, with a resolution Figure of Merit (FoM) of 0.85

BJT-based temperature sensors are widely used due to their high accuracy over a wide temperature range with a low-cost 1-point trim. Although resistor-based sensors can achieve better energy efficiency, they typically require a 2-point trim to achieve comparable accuracy, while thermal-diffusivity based sensors achieve superior accuracy at the cost of energy efficiency [1]. This paper presents a BJT-based temperature sensor that achieves both excellent accuracy and energy efficiency. To avoid the kTfC noise limitations of conventional discrete-time (OT) readout schemes [2], [3], it employs a compact continuous-time (CT) front-end. Component mismatch, which often limits the accuracy of CT front-ends [4], [5], is mitigated by a combination of dynamic element matching (OEM) and a low-cost resistor-ratio self-calibration scheme. As a result, the sensor achieves a resolution FoM of 0.85textpJcdotK 2, and a competitive inaccuracy of pm 0.1 circC (3sigma) from -55 circC tO 125 circC after a 1-point trim. This makes it 4times more energy-efficient than state-of-the-art BJT-based sensors with similar accuracy [2], [4], [5].

This letter describes an NPN-based temperature sensor that achieves a 1-point trimmed inaccuracy of ±0.15 °C (3σ) from -15 to 85 °C while dissipating only 210 nW. It uses a dual-mode frontend to roughly halve the power consumption of conventional frontends. First, two NPNs are used to generate a well-defined PTAT bias current, then this current is sampled and applied to the same NPNs to generate well-defined PTAT and CTAT voltages. These voltages are then applied to a low-power tracking ΔΣ modulator-based ADC, which employs a digital filter to efficiently generate a multibit representation of temperature. A prototype fabricated in a 180-nm BCD process achieves 15-mK resolution in a 50 ms conversion time, which translates into a state-of-the-art resolution FoM of 2.3 pJK2.

This paper presents a 210nW BJT-based temperature sensor that achieves an inaccuracy of ±0.15°C (3s) from -15°C to 85°C. A dual-mode front-end (FE), which combines a bias circuit and a BJT core, halves the power needed to generate well-defined CTAT (VBE) and PTAT (?VBE) voltages. The use of a tracking ?S ADC reduces FE signal swing and further reduces system power consumption. In a 180-nm BCD process, the prototype achieves a 15mK resolution in 50ms conversion time, translating into a state-of-the-art FoM of 2.3pJK2.

In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-N multiplying delay-locked loop,(MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed, and a two-stage synthesizable DTC is proposed in which a path-selection DTC is used as the coarse stage and a variable-slope DTC is used as the fine stage. To calibrate the DTC nonlinearity, a highly robust zero-order interpolation based nonlinearity calibration is proposed. Besides, the static phase offsets,(SPO) between bang-bang phase detector,(BBPD) and multiplexer,(MUX) are calibrated by a proposed hybrid analog/digital phase offset calibration, while the dynamic phase offsets,(DPO) are removed by a proposed complementary switching scheme. The co-design of the analog circuits and digital calibrations enable excellent jitter and spur performance. The MDLL achieves 0.70 and 0.48,ps root-mean-square,(RMS) jitter in fractional-N and integer-N modes, respectively. The fractional spur is less than -59.0,dBc, and the reference spur is -64.5,dBc. The power consumptions are 1.85,mW and 1.22,mW, corresponding to figures of merit,(FOM) of -240.4,dB and -245.5,dB.

A 6.4 nW 1.7% relative inaccuracy (R-IA) CMOS sub-thermal drain voltage-based temperature sensor is proposed. The proposed stabilized sub-thermal drain voltage current generator achieves a highly linear PTAT output without nonlinearity fitting or post-fabrication trimming and increases the accuracy of the sensor. A combination of the current generator and a frequency-locked loop relaxes the tradeoff between power and temperature stability of the current-to-frequency converter and achieves supply voltage-independent operation. Measured results of the prototype fabricated in a 65-nm CMOS process show that the proposed temperature sensor has a -1.0/+0.7 °C inaccuracy (= R-IA of 1.7%) while achieving a resolution of 75 mK over a temperature range of -30 °C to 70 °C. The line sensitivity of the sensor is 2.8 °C/V.