A 6.4 nW 1.7% Relative Inaccuracy CMOS Temperature Sensor Utilizing Sub-thermal Drain Voltage Stabilization and Frequency Locked Loop
T. Someya (Tokyo Institute of Technology, TU Delft - Electronic Instrumentation)
A. K.M.Mahfuzul Islam (Kyoto University)
Kenichi Okada (Tokyo Institute of Technology)
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Abstract
A 6.4 nW 1.7% relative inaccuracy (R-IA) CMOS sub-thermal drain voltage-based temperature sensor is proposed. The proposed stabilized sub-thermal drain voltage current generator achieves a highly linear PTAT output without nonlinearity fitting or post-fabrication trimming and increases the accuracy of the sensor. A combination of the current generator and a frequency-locked loop relaxes the tradeoff between power and temperature stability of the current-to-frequency converter and achieves supply voltage-independent operation. Measured results of the prototype fabricated in a 65-nm CMOS process show that the proposed temperature sensor has a -1.0/+0.7 °C inaccuracy (= R-IA of 1.7%) while achieving a resolution of 75 mK over a temperature range of -30 °C to 70 °C. The line sensitivity of the sensor is 2.8 °C/V.