In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-N multiplying delay-locked loop,(MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed, and a two-stage synthesizable DTC is proposed in which a path-selection DTC is used as the coarse stage and a variable-slope DTC is used as the fine stage. To calibrate the DTC nonlinearity, a highly robust zero-order interpolation based nonlinearity calibration is proposed. Besides, the static phase offsets,(SPO) between bang-bang phase detector,(BBPD) and multiplexer,(MUX) are calibrated by a proposed hybrid analog/digital phase offset calibration, while the dynamic phase offsets,(DPO) are removed by a proposed complementary switching scheme. The co-design of the analog circuits and digital calibrations enable excellent jitter and spur performance. The MDLL achieves 0.70 and 0.48,ps root-mean-square,(RMS) jitter in fractional-N and integer-N modes, respectively. The fractional spur is less than -59.0,dBc, and the reference spur is -64.5,dBc. The power consumptions are 1.85,mW and 1.22,mW, corresponding to figures of merit,(FOM) of -240.4,dB and -245.5,dB.