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A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration

Journal Article (2021)
Author(s)

Bangan Liu (Tokyo Institute of Technology)

Yuncheng Zhang (Tokyo Institute of Technology)

Junjun Qiu (Tokyo Institute of Technology)

Huy Cu Ngo (Tokyo Institute of Technology)

Wei Deng (Tsinghua University)

Kengo Nakata (Tokyo Institute of Technology)

Toru Yoshioka (Tokyo Institute of Technology)

Jun Emmei (Tokyo Institute of Technology)

Jian Pang (Tokyo Institute of Technology)

T. Someya (TU Delft - Electronic Instrumentation)

More Authors (External organisation)

Research Group
Electronic Instrumentation
Copyright
© 2021 Bangan Liu, Yuncheng Zhang, Junjun Qiu, Huy Cu Ngo, Wei Deng, Kengo Nakata, Toru Yoshioka, Jun Emmei, Jian Pang, T. Someya, More Authors
DOI related publication
https://doi.org/10.1109/TCSI.2020.3035373
More Info
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Publication Year
2021
Language
English
Copyright
© 2021 Bangan Liu, Yuncheng Zhang, Junjun Qiu, Huy Cu Ngo, Wei Deng, Kengo Nakata, Toru Yoshioka, Jun Emmei, Jian Pang, T. Someya, More Authors
Research Group
Electronic Instrumentation
Issue number
2
Volume number
68
Pages (from-to)
603 - 616
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Abstract

In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-N multiplying delay-locked loop,(MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed, and a two-stage synthesizable DTC is proposed in which a path-selection DTC is used as the coarse stage and a variable-slope DTC is used as the fine stage. To calibrate the DTC nonlinearity, a highly robust zero-order interpolation based nonlinearity calibration is proposed. Besides, the static phase offsets,(SPO) between bang-bang phase detector,(BBPD) and multiplexer,(MUX) are calibrated by a proposed hybrid analog/digital phase offset calibration, while the dynamic phase offsets,(DPO) are removed by a proposed complementary switching scheme. The co-design of the analog circuits and digital calibrations enable excellent jitter and spur performance. The MDLL achieves 0.70 and 0.48,ps root-mean-square,(RMS) jitter in fractional-N and integer-N modes, respectively. The fractional spur is less than -59.0,dBc, and the reference spur is -64.5,dBc. The power consumptions are 1.85,mW and 1.22,mW, corresponding to figures of merit,(FOM) of -240.4,dB and -245.5,dB.