In chopper amplifiers, the interaction between the input signal and the chopper clock can cause intermodulation distortion (IMD). This is due to amplifier delay, which causes signal transitions generated by the input chopper to arrive at the amplifier's output slightly later than the corresponding clock transitions of the output chopper. This causes large signal-dependent spikes in the final output, which can significantly degrade amplifier linearity, especially at input frequencies near even multiples of the chopping frequency FcH, which will cause IMD tones near DC. In [2-4], spread-spectrum clocks are used to convert such tones into noise-like signals. However, this increases the noise floor, without solving the underlying problem. Recently, it has been shown that such spikes can be eliminated by using the fill-in technique [1], in which two identical OTAs are chopped in quadrature, allowing a spike-free output to be generated by switching between their outputs in a ping-pong fashion.

In chopper amplifiers, the interaction between the input signal and the chopper clock can cause intermodulation distortion (IMD). This is mainly due to finite amplifier bandwidth, which causes signal-dependent output spikes at the chopping transitions. Such chopper-induced IMD can be mitigated by the fill-in technique, which involves ping-ponging between the outputs of two identical OTAs chopped in quadrature, thus generating a spike-free output. In this letter, a relaxed implementation is proposed in which the output of a fill-in OTA is only briefly used to avoid the spikes of a chopped main OTA. As a result, the fill-in OTA does not need to be chopped, and so it can be duty-cycled to save power. Furthermore, the chopper ripple caused by the main OTA can now be suppressed by a single low-noise ripple-reduction loop, rather than the two AZ loops required in a previous ping-pong implementation of the fill-in technique. Compared to the latter, the proposed amplifier achieves similar IMD performance (-125.7 dB), a 25× lower input current (22.6 pA), and a flat noise floor (12 nV/ Hz).

This article describes an auto-zero stabilized voltage buffer that achieves low offset and low noise with sub-pA input current. A high gain stabilization loop is used to periodically cancel the buffer’s offset. The loop itself is periodically disconnected from the buffer and auto-zeroed, during which its bandwidth is reduced to reduce the associated noise folding. However, this also reduces its offset correction range, and so to avoid overloading, its initial offset is digitally trimmed. To break up the correlation between the residual low-frequency (LF) noise of the auto-zero and stabilization phases, the loop is periodically chopped, which significantly reduces the buffer’s LF noise. Finally, the duty-cycle of the two phases is optimized to bring the buffer’s LF noise density close to 2–√ times its white noise density (14 nV/ Hz−−−√ ), which is the fundamental limit of an AZ amplifier. The buffer also achieves a constant and low input current (0.8 pA), as well as a state-of-the-art offset (0.4 μV ).

Amplifiers often employ chopping to achieve low offset and low-frequency noise. However, the interaction between the input signal and the chopper clock can cause chopper-induced intermodulation distortion (IMD) [1] -[5]. This is especially problematic for input frequencies (Fin) near even multiples of the chopping frequency (FCH), as the resulting IMD tones fold-back to low frequencies and so cannot be filtered out. In [2] -[4], spread-spectrum clocks are used to convert such tones into noise-like signals. However, this increases the noise floor and does not address the underlying problem. This paper shows that chopper-induced IMD is mainly due to amplifier delay, which results in large chopping spikes. A novel fill-in technique is proposed that mitigates these spikes, and so reduces the chopper-induced IMD. In a prototype chopper-stabilized amplifier, it reduces the chopper-induced IMD by 28dB, resulting in an IMD of -126dB for input frequencies near 4FCH (=80kHz). Similarly, it improves the chopped amplifier's two-tone IMD (79 and 80kHz) from -97dB to -107dB, thus maintaining the same IMD as the un-chopped amplifier.

The readout of high-impedance sensors and sampled voltage references [1] requires amplifiers that can achieve both low offset and low input current. Recently, it has been shown that this unique combination can be achieved by an auto-zero (AZ) stabilized buffer [2]. However, its low-frequency noise density is surd 5 times higher than the buffer's own white-noise voltage spectral density e _n . Furthermore, its input current is not constant, but varies significantly with the input voltage. To overcome the first issue, a chopped AZ stabilization loop with an optimized duty-cycle is proposed to bring the low-frequency noise density close to surd 2cdot {e}-{n}, the fundamental limit of an AZ stabilized amplifier. The second issue is solved by replacing the transmission-gate input switches used in [2] with NMOS switches and a constant Vgs drive. This keeps their charge injection constant over a wide input voltage range, and results in a constant input current.

A low-power class-AB amplifier for high-fidelity headphones is presented. The linearity of a class-AB amplifier strongly depends on the loop gain over the audio band and voltage swing. In this paper, a cascode-driven mesh technique limits the number of high-swing nodes in the output stage, thereby preserving the loop gain of the preceding gain stages. A frequency compensation scheme is proposed that extends the unity-gain bandwidth (UGB) and increases the loop gain at 20 kHz. Combining these two techniques, the amplifier achieves -101.4-dB total harmonic distortion plus noise (THD+N) over the full audio band, the lowest ever reported nonlinearity among sub-milliwatt CMOS class-AB amplifiers. The amplifier delivers 51.2-mW peak power to a 16Ω 0.33 -nF load while consuming 0.97 mW of total static power. It has UGB of 12.3 MHz and SNR of 108 dB. These results are consistent when measured over eight test chips. Compared to the recent prior art, the amplifier exhibits >12 dB better linearity and >14-dB dynamic range. This results in 2.5 × improvement in figure of merit (FOM = Peak Load Power/(Quiescent Power × THD+N[%])). It occupies 0.16 mm ² in a standard 65-nm CMOS.

This paper presents an input-current trimming scheme for auto-zero amplifiers. Since their input current is mainly due to charge injection,the scheme operates by trimming the clock swing,and hence the charge injection,of two dummy input switches. At room temperature,the trimming scheme reduces the maximum input current of an auto-zero stabilized voltage buffer from 1pA to 0.2pA (13 samples) over its full input voltage range (0 to 1.3V). This increases to 0.4pA over temperature (0 to 85°C),which is well below the leakage of typical ESD diodes,and is the lowest input current ever reported for an auto-zero amplifier.

This paper presents a class-AB driver for high-fidelity audio. It attains high-linearity at low-power by using an improved output stage biasing technique and a new frequency compensation scheme. Designed in standard 65nm CMOS, the driver delivers 5I.2mW peak power to 16Ω 0.33nF load, while consuming 0.97mW. It achieves -101.4dB THD+N over full audio band, the lowest ever reported linearity among sub-milliwatt CMOS class-AB drivers. Compared to prior works, it has >12dB better linearity and >7x higher unity-gain bandwidth, resulting in 2.5x improvement in linearity FOM (=Peak Load Power/ (Quiescent Power × THD+N[%])).

This paper presents a fully integrated ±4A current sensor that supports a 25V input common-mode voltage range (CMVR) while operating from a single 1.5V supply. It consists of an on-chip metal shunt, a beyond-the-rails ADC [1] and a temperature-dependent voltage reference. The beyond-the-rails ADC facilitates high-side current sensing without the need for external resistive dividers or level shifters, thus reducing power consumption and system complexity. To compensate for the shunt's temperature dependence, the ADC employs a proportional-to-absolute-temperature (PTAT) reference voltage. Compared to digital temperature compensation schemes [2,3], this analog scheme eliminates the need for a temperature sensor, a band-gap voltage reference and calibration logic. As a result, the current sensor draws only 10.9μA and is 10x more energy efficient than [2]. Over a ±4A range, and after a one-point trim, the sensor exhibits a 0.9% (max) gain error from -40°C to 85°C and a 0.05% gain error at room temperature. The former is comparable with that of other fully-integrated current sensors [2-4], while the latter represents the state-of-the-art.

This paper presents an NPN-based temperature sensor intended for the temperature compensation of the metal shunt resistor of an integrated current sensing system. The sensor was implemented in a 0.18 HV BCD CMOS technology and occupies 0.16mm² After a one-point trim, its inaccuracy is less than ±0.4°C over the industrial temperature range (-40°C to 85°C). It also achieves 14.8niK resolution in a 7ms conversion time while consuming 12μm. This results in a resolution FOM of 18.4pJ·K² the lowest ever reported for an NPN-based sensor.