JH
J.H. Huijsing
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3 records found
1
A chopper-stabilized amplifier using a novel embedded fill-in technique and a low-distortion RRL has been designed in TSMC 180nm BCD technology. The embedded fill-in technique covers the chopper-induced glitches to improve the even-order IMD tones of the amplifier. An optimized RRL is proposed to further reduce even-order IMD. The amplifier achieves an offset and ripple tone of 0.41μV and -111.2dBV respectively, with an even-order IMD of -120dBV over the signal bandwidth.
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A chopper-stabilized amplifier using a novel embedded fill-in technique and a low-distortion RRL has been designed in TSMC 180nm BCD technology. The embedded fill-in technique covers the chopper-induced glitches to improve the even-order IMD tones of the amplifier. An optimized RRL is proposed to further reduce even-order IMD. The amplifier achieves an offset and ripple tone of 0.41μV and -111.2dBV respectively, with an even-order IMD of -120dBV over the signal bandwidth.
CMOS amplifiers suffer from offset (several mVs), offset drift (several µV/°C) and 1/f noise corner (tens of kHz). Dynamic offset compensation (DOC) techniques, such as auto-zeroing and chopping, are often used to achieve low offset (µV level), offset drift (< 20 nV/°C) and 1/f noise corners (several Hz). However, these techniques also have drawbacks, mainly due to the required input switching. This results in unwanted spikes, input current and intermodulation distortion. This thesis presents DOC amplifiers with sub-pA input current, low distortion, as well as quiet outputs.
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CMOS amplifiers suffer from offset (several mVs), offset drift (several µV/°C) and 1/f noise corner (tens of kHz). Dynamic offset compensation (DOC) techniques, such as auto-zeroing and chopping, are often used to achieve low offset (µV level), offset drift (< 20 nV/°C) and 1/f noise corners (several Hz). However, these techniques also have drawbacks, mainly due to the required input switching. This results in unwanted spikes, input current and intermodulation distortion. This thesis presents DOC amplifiers with sub-pA input current, low distortion, as well as quiet outputs.
A Bootstrapped ESD Structure for CMOS Amplifiers with femtoampere leakage current
A Bootstrapped ESD Structure for CMOS Amplifiers with femtoampere leakage current
Integrated circuits (ICs) are susceptible to damage by Electrostatic Discharge (ESD), which necessitates protection diodes. However, these diodes can cause leakage currents in the range of picoamperes, dominating the input current of CMOS ICs. This thesis presents the implementation of a low leakage bootstrapped ESD protection circuit for amplifiers with low input currents. An auxiliary buffer connected to the input pad is used to drive the voltage across the ESD protection diodes to a near-zero value, thus ensuring leakage currents in the femtoampere range. Two kinds of protection diode structures were designed and characterized. Based on the results, an auxiliary buffer was designed to bootstrap the diodes. Next, the bootstrapped ESD diode structure was taped out and measured. A low leakage test PCB was designed using techniques such as guarding, shielding, and via-fencing, resulting in bare PCB leakage currents well below 20 fA. The ESD protection circuit is fabricated in TSMC 180 nm MS/RF CMOS technology and occupies an area of 0.043mm2. With this circuit, input leakage currents below 150fA have been measured.
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Integrated circuits (ICs) are susceptible to damage by Electrostatic Discharge (ESD), which necessitates protection diodes. However, these diodes can cause leakage currents in the range of picoamperes, dominating the input current of CMOS ICs. This thesis presents the implementation of a low leakage bootstrapped ESD protection circuit for amplifiers with low input currents. An auxiliary buffer connected to the input pad is used to drive the voltage across the ESD protection diodes to a near-zero value, thus ensuring leakage currents in the femtoampere range. Two kinds of protection diode structures were designed and characterized. Based on the results, an auxiliary buffer was designed to bootstrap the diodes. Next, the bootstrapped ESD diode structure was taped out and measured. A low leakage test PCB was designed using techniques such as guarding, shielding, and via-fencing, resulting in bare PCB leakage currents well below 20 fA. The ESD protection circuit is fabricated in TSMC 180 nm MS/RF CMOS technology and occupies an area of 0.043mm2. With this circuit, input leakage currents below 150fA have been measured.