A 10kHz-BW 93.7dB-SNR Chopped ΔΣ ADC with 30V Input CM Range and 115dB CMRR at 10kHz

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A 10kHz-BW 93.7dB-SNR Chopped ΔΣ ADC with 30V Input CM Range and 115dB CMRR at 10kHz

Conference Paper (2017)

Author(s)

Long Xu (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Johan H. Huijsing (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Kofi A.A. Makinwa (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Research Group

Electronic Instrumentation

CMRR Chopping ΔΣ ADC Beyond-the-rails

DOI related publication

https://doi.org/10.1109/ASSCC.2017.8240213 Final published version

To reference this document use

https://resolver.tudelft.nl/uuid:f2bba6c3-7bea-43b8-ab73-45ce6b5e5f9d

More Info

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Publication Year

2017

Language

English

Research Group

Electronic Instrumentation

Pages (from-to)

49-52

ISBN (electronic)

978-1-5386-3178-2

Event

A-SSCC 2017 (2017-11-06 - 2017-11-08), Grand Hilton Hotel, Seoul, Korea, Republic of

Downloads counter

162

Abstract

This paper presents a 15-bit ΔΣ ADC with 10kHz-BW which can handle 30V CM voltages with high AC CMRR (in excess of 115dB at 10kHz) while operating from a 1.8 V supply. An HV capacitively-coupled chopper at its input enables the accurate sampling of input signals beyond the supply rails. Chopping is used to mitigate the ADC's offset and to enhance its CMRR, especially at high frequencies.