This thesis presents a PNP-based temperature sensor that employs an energy-efficient current–voltage mirror (CVM) front-end. In contrast to prior PNP-based designs that rely on a low-noise but power-hungry bias amplifier, the proposed architecture replaces the amplifier with a symmetrically matched CVM, substantially reducing power consumption while preserving comparable noise performance. The PTAT voltage is generated using an emitter-area ratio rather than a current ratio, further improving energy efficiency. To suppress mismatch, flicker noise, and offset-related errors, several dynamic techniques—including bitstream-controlled DEM, chopping, and resistor-ratio calibration—are incorporated into the system. Simulated in a 0.18-μm CMOS process, the design achieves a resolution FoM of 0.558 pJ·K2, with a resolution of 1.97 mK at a 38.4 ms conversion time. It attains an inaccuracy of 0.1◦C (3σ) over the −55◦C to 125◦C temperature range after one-point trimming, while consuming only 3.75 ¯W. These results demonstrate that CVM-biased front-ends provide a promising direction for next-generation ultralow-power PNP temperature sensors.