This letter describes a fast-settling active rectifier for a 40.68 MHz wireless power transfer receiver for implantable applications. Fast-settling and low power are achieved through a novel direct voltage-domain compensation technique. The rectifier maintains high efficiency during load and link variations required for downlink communication. The system was fabricated in 40nm CMOS and achieves a voltage conversion ratio of 93.9% and a simulated power conversion efficiency of 90.1% in a 0.19 mm² area, resulting in a 118 mW/mm² power density while integrating the resonance and filter capacitors. The worst-case settling of the ON-and OFF-delay compensation in the active rectifier is 200 ns, which is the fastest reported to date.

This paper presents a fully-integrated single-input dual-output power management unit operating both in volt age/current modes for powering mm-scale wireless neural im plants. The chip operates in voltage mode most of the time, using an active full-wave rectifier to regulate a low-voltage, high load output with high power efficiency and low output ripple (<32 mV_pp). It switches to current mode rectification when gen erating a high-voltage, low-load output. This dual-mode operation allows for flexible power distribution and configurable voltage ratios between the two outputs. The selected 40.68 MHz operating frequency reduces the required capacitances for input impedance matching and output filtering, enabling on-chip integration; the only external component is the receiver coil. A novel resonance breakup switch compatible with full-wave rectification ensures a smooth cold start-up of the chip without any external voltage supply. The chip was fabricated using 40-nm CMOS technology with an active area of 1.18 mm² and was tested in a wireless power link. Measurement results demonstrate that the chip can simultaneously regulate two outputs, V_LV = 1 V and V_HV = 2 V, with a tested maximum output power of 10 mW and 32.6 µW on V_LV and V_HV, respectively. At the optimal output power condition (P_LV = 4.4∼6.7 mW), the system achieves a peak power conversion efficiency of 85.87% and a peak end-to-end efficiency of 17.32% when regulating V_LV. The end-to-end efficiency drops by only 2.38% when regulating both outputs with R_LV = 225 Ω and R_HV = 400 kΩ.

Brain-computer interfaces of the future will be recorded from tens of thousands of high-density electrodes. This paper presents a neural amplifier for next-generation single-cell resolution BCIs. The amplifier leverages spatial signal correlation to introduce a novel shared DC servo loop to improve area efficiency while maintaining state-of-the-art power efficiency. Post-layout simulations in 40 nm CMOS technology achieve a 50 dB gain in a [0.1-5.2] kHz bandwidth. The amplifier consumes 920 nW and achieves a total input-referred noise of 8 μ V_rms while occupying only 35 μ m × 35 μ m per recording channel.