To achieve greater specificity in neurostimulation, bidirectional neural interfaces are required to verify the recorded neural response after stimulation. The specific neural interface targeted in this thesis is the epiretinal implant. Due to the heterogeneity of the retinal ganglion cells (RGCs), high-fidelity vision is only possible when all the types of RGCs near the neurostimulator are mapped. This necessitates the bidirectionality of the implant and poses significant difficulties, as large stimulation artifacts obscure the small neural response that needs to be recorded. Furthermore, in order to cover a large area of the retina, a channel count in the order of 104 will be required. Scaling existing neurostimulators would lead to chips that are >30mm2, which is too large. The aim of this thesis is therefore to design a neurostimulator for the epiretinal implant that is capable of implementing artifact-reducing algorithms, and is smaller than the current state-of-the-art. The proposed system makes use of a mismatch-based digital-to-analog converter (DAC), and has been optimized for an output range of 0-6 μA at an effective resolution of 8-bits. Furthermore, in order to decrease the amount of stimulation units required, waveform interleaving has been proposed, where the anodic and cathodic stimulator are separated. A voltage compliance monitor is also designed to ensure proper stimulation output. The designed system has been fabricated and occupies 0.0003mm2 for two channels. Scaling this directly to 104 channels would result in an area of 1.645mm2. This area can be reduced even further via electrode multiplexing, which the designed system readily allows for. An output availability (i.e. how many input codes are possible after calibrating) of 99.2% and 97.3% is reported for the anodic and cathodic stimulator at an 8-bit resolution over the full output range.

Bidirectional neural recording ICs faces the challenge of simultaneous stimulation and recording. The recording IC should endure large stimulation artifacts while capturing weak neural signals excited by the stimuli. The stimulation artifacts can be as large as hundreds of millivolts, which can saturate the recording front end. Conventional neural-recording ICs use a low-noise-amplifier (LNA), a programmable-gain amplifier (PGA) followed by an analog-to-digital converter (ADC), leading to low power consumptions and great noise performances. However, the dynamic range (DR) is usually limited to 50 dB. State-of-the-art recording ICs using direct-conversion ADCs have been intro- duced to increase the DR. However, the typical power and area consumption for these architectures are exceeding the requirements for next-generation brain-computer interfaces. This work proposes a novel neural-recording IC system architecture with satu- ration prevention in presence of large stimulation artifacts. The proposed architecture consists of an AC-coupled boxcar sampler, switched-capacitor low-pass filter followed by a 10-bit asynchronous SAR ADC. The integrated voltage at the output of the boxcar sampler is sampled by the ADC and monitored by a level-cross detection block. Based on the output of the level-cross detection block, the integration time, and thus the gain, can be tuned to different configurations pre-defined in a look-up table (LUT). The additional noise penalty due to noise-folding from decreasing the integration time is compensated by oversampling and averaging. The proposed system architecture is partially imple- mented at transistor level while the ADC and digital blocks are modeled using verilog-A as a proof-of-concept. The analog front-end achieves a DR of 69.5 dB with a peak-to-peak maximum input amplitude of 180 mVPP and a typical ENOB of 8.01 bits.