This Ph.D. dissertation focuses on designing high-precision readout frontends for low energy charge detection in scanning electron microscopy (SEM), achieving a time resolution of 2.5 ns, a detection error rate below 6 ppm, and power consumption under 400 μW. Novel techniques at both the system and circuit levels were developed to enhance operational accuracy and meet the target specifications. Two prototypes were presented and experimentally tested to demonstrate the effectiveness of these techniques.
Chapter 1 introduces the motivation, research objectives, and organization of the thesis, highlighting the advancements in SEMs for nanometer-resolution imaging and the challenges posed by high scanning speeds. It emphasizes the need for sensitive detectors and low-noise, power-efficient readout electronics, which often conflict. The main research question is defined as developing a frontend readout architecture with power consumption below 500 μW, time resolution of 2.5 ns, and an electron count error under 10 ppm. To address this, the thesis employs a systematic study and iterative design process, resulting in two novel readout frontend architectures. The chapter also outlines the structure of the thesis, covering the operating principles of the PIN diode, design details, experimental evaluations, and conclusions.
Chapter 2 provides a detailed review of the target application specifications, focusing on the design and requirements for detecting weak charge signals with high precision and time resolution. It critically analyzes the current state-of-the-art readout frontends, highlighting their strengths and inherent limitations, particularly in terms of noise performance, time resolution, and power consumption. This chapter also introduces the concept of short and open circuit readout modes for PIN-diodes, offering insights into their potential advantages for addressing the challenges identified in the existing systems.
Chapter 3 presents the design of readout solutions for the short circuit operation mode of PIN-diodes, critical for BSE detection in electron microscopy. It examines the use of a preamplifier to create a virtual ground, effectively simulating a zero-impedance load and ensuring accurate charge transfer. The chapter further explores the analog frontend components: preamplifier, signal shaping filters, and threshold discriminators. Signal shaping filters, both passive and active high-pass types, are discussed for their role in signal optimization by reducing noise and improving signal clarity. Additionally, the threshold discriminator design is analyzed for both filter types, emphasizing the importance of accurate signal discrimination to minimize detection errors. A key focus is the tradeoff between power consumption, noise performance, and detection accuracy, with each stage's design detailed to ensure optimal performance and signal integrity in the short circuit mode.
Chapter 4 explores readout solutions for the open circuit mode of PIN-diodes, focusing on high sensitivity, low power consumption, and signal integrity. It highlights challenges like charge pileup and saturation, proposing solutions such as a reset mechanism and dynamic comparators. The chapter discusses an advanced frontend architecture with offset compensation and active capacitor matching for improved accuracy. Periodic sampling at 800 MHz minimizes timing misalignments, balancing power efficiency and reliability for high-resolution, high-rate applications.
Chapter 5 discusses the experimental setup and qualification of the proposed readout architectures. The device under test (DUT), a 40 nm CMOS chip with short and open circuit mode readout matrices, is tested to validate its ability to detect and digitize charge signals within the specified power budget. The test includes evaluating performance across gain, noise, bandwidth, and threshold levels, using a programmable detector emulating circuit (DEC) to simulate charge signals. The setup features a FPGA-based Data Acquisition Board (DAB) for signal monitoring and a test PCB to run experimental qualifications.
Chapter 6 concludes the thesis by highlighting the development of advanced readout frontends for high-precision charge detection, achieving improved time resolution, accuracy, and power efficiency. The proposed designs, optimized for short circuit and open circuit modes, demonstrate excellent performance. This chapter also proposes and discusses some aspects of this work that could be explored for further improvements.

Due to the rapid development of smart homes, some low-power consumption appliances need AC mains to supply energy, so the demand for AC-DC converters is increasing. AC-DC converters using transformers are not suitable for low-power devices due to their large size and expensive price. The method of series capacitors is a good way to convert high-voltage AC to low-voltage DC but has the disadvantage of low output power.
In this report, a Short-Flip Switched-Capacitor-Based AC-DC Converter for 120/230 VRMS mains Interfaces is proposed. Its innovative use of two charge-clearing switches clears the remaining charge of the switched capacitor after each closure. In this way, the same small voltage drops when the switched capacitor is needed to be connected, which ensures a long conduction time. In addition, two switches are used for short-flip operation, so that the waveform after the capacitor divider can be quickly lowered to 0 voltage, which can move to the next half-period faster, and applying these two switches can improve the maximum output power by 15%. The proposed AC-DC converter was manufactured in the 180 nm BCD process, with a silicon area of 2 mm2. It was tested and achieved a maximum output power of 1.2W and a peak efficiency of 78%, the power density is 1100mW /cm2, which is better than the state-of-art.

This thesis presents the development of a high-efficiency, high-power output multi-path resonant DC-DC converter, designed to meet the growing demands of modern electronic systems that require robust load capability and effective thermal management. The proposed converter architecture leverages advanced semiconductor technologies, innovative design strategies, and optimized control techniques to achieve exceptional power density and efficiency.

In addressing the challenges associated with heat dissipation in high-power converters, the research focuses on minimizing power loss, which directly impacts the reliability and longevity of electronic components. The converter targets a frequency efficiency of 96.5%, ensuring optimal performance across a wide output range.

The work begins with a comprehensive review of existing DC-DC converter types, including their advantages and limitations. This sets the stage for the introduction of a novel multi-path resonant converter topology, which combines the strengths of inductive and capacitive conversion techniques to reduce conduction losses and enhance overall efficiency.

Control techniques for powering floating gate drivers are also explored, providing the necessary support for the converter’s operation under varying load conditions. The design is validated through extensive simulations, demonstrating the converter’s ability to handle high currents while maintaining high efficiency. A PCB prototype is also developed to further validate the proposed design.

The results of this research indicate that the proposed converter not only meets but exceeds current performance benchmarks, offering a viable solution for high-power density applications in data centres, telecommunications, and other industrial systems.

As wireless communication systems grow more complex, especially with the advent of 5G networks, the demand for efficient digital predistortion (DPD) techniques to improve the linearity and performance of power amplifiers (PAs) is increasing. Advanced neural network hardware accelerators like EdgeDRNN offer promising solutions to these challenges by enhancing computational efficiency and accuracy. This thesis provides a detailed evaluation of the EdgeDRNN hardware accelerator, which is applied by the OpenDPD network to tackle the common issues of computational complexity and parameter management that often impede DPD implementations. By employing high-level synthesis (HLS) for the linear layer within the EdgeDRNN model, the performance metrics can be improved. Through our research, we estimate the performance of the combined system, which has a latency of 6.50 microseconds and a throughput of 0.26 giga-operation per second. The study highlights EdgeDRNN’s performance and scalability, particularly in its ability to adapt to future wireless standards like 5G. However, the research also identifies some limitations on the performance, which sets a stage for future exploration. By designing and optimizing a new hardware accelerator for DPD, this work enables ultra-high-speed DPD solutions for next-generation wireless communication systems.

With the development of the Internet of Things (IoT) and biomedical technologies, the utilization of wearable devices has become an emerging trend, attracting attention to the powering solutions for these devices. Thermoelectric energy harvesting (TEH) is suitable for converting the temperature difference in the ambient environment to power wearable devices and IoT sensors. However, the DC voltage converted by the thermoelectric generator (TEG) still requires an energy harvesting interface, normally a DC-DC interface to provide the regulated power to the load. Consequently, the features of the TEG impose challenges to the implementation of the DC-DC interface. Due to the temperature dependency of the TEG, the DC-DC interface applied to the TEH system should be able to cope with the dual-polarity input voltage and be capable of achieving a high power conversion efficiency for a wide range of voltage conversion ratios.

As the use of Internet-of-Things (IoT) devices in medical treatment and health moni toring continues to expand, traditional battery-powered sensors are becoming increas ingly inadequateduetothechallengesassociatedwithbatteryreplacement,whichoften necessitates additional surgeries and medical care. In contrast, thermoelectric energy harvesting (TEH) systems, which convert ambient thermal energy into electrical energy, offer a sustainable solution for wearable devices. TEH systems, known for their high energy density and flexibility, have the potential to make IoT devices self-powered by utilizing ambient thermalenergy. However,itisdifficulttoefficiently extract powerfrom low-temperature gradients. Previous studies have only achieved high energy-harvesting efficiency within limited ranges of thermoelectric generator (TEG) voltage (VTEG) and TEG internal resistance (RTEG). This limitation arises due to the high power consump tion of control systems, which consume a significant portion of the harvested energy, particularly under low VTEG and high RTEG conditions. To address these challenges, an interface for TEH systems with ultra-low power consumption and precise control mod ules is urgently needed. This project is divided into two parts. The first part involves summarizing and com paring the state-of-the-art in TEH, with a focus on advanced techniques used in other TEH systems and the potential for ultra-low power consumption. The remainder of the thesis proposes an all-digital controlled TEH interface that incorporates SAR zero current sensing (ZCS) and digital Maximum Power Point Tracking (MPPT). Theoretical analysis, designdetails, andmeasuredperformanceofthissystem—thefirstfullydigital controlled TEHsystem—arethoroughlydiscussed. Thechiphasalreadybeenfabricated andtested

This paper reviews recent developments in the transmitter end of wireless power transfer (WPT) systems, focusing on the limitations of current solutions in addressing variations in the real part of the load resistance. Traditional Class D inverters are limited in high-frequency integrated circuit applications due to issues with parasitic capacitance charging/discharging and dead-time. While Class E inverters are more suitable for highfrequency applications, they are highly sensitive to load variations. To address this challenge, this paper proposes an impedance matching network based on dual-loop negative feedback, which can adjust in real-time according to changes in load resistance, thereby stabilizing output efficiency under varying load conditions. Through circuit design and simulation, the system achieves a maximum output efficiency of 95.16% at 100W output power and can accommodate variations in both the real and imaginary parts of the load, making it suitable for WPT system receivers with variable loads.

Piezoelectric (PE) and electromagnetic (EM) methods are two popular techniques for harvesting kinetic vibration energy. When combined, these methods can power self-sustaining wireless sensors that require higher power consumption. However, existing hybrid energy systems necessitate at least one large off-chip inductor for either bias-flip or DC-DC conversion. This large inductor significantly increases the system's volume, leading to integration issues in space-constrained Internet-of-Things (IoT) applications.
This thesis proposes a fully integrated PE-EM hybrid energy harvesting platform to address this issue. By properly arranging synchronous PE and EM phases, the new active-to-passive coil-sharing technique eliminates the need for an additional energy reservoir for bias-flip and DC-DC. The IC prototype, fabricated using the 0.18um BCD CMOS process, has been experimentally tested. Results show a flipping efficiency of up to 70%. Additionally, the proposed single-stage system structure allows the output to be parallel with the battery stage, achieving high end-to-end (E2E) efficiency.

Micro-Electro-Mechanical Systems (MEMS) resonators have gained widespread application in high-precision sensors across various industries, including wearable devices,
automotive systems, and consumer electronics. This popularity stems from their advantages such as high precision, high resolution, small size, and ease of integration. However, despite these advantages, the circuit designs for MEMS resonators—specifically the
sustaining oscillator circuits—have remained largely unchanged for decades. Traditional
excitation methods have faced limitations, particularly in terms of low output amplitude
and restricted linearity of the MEMS devices. These constraints present challenges in improving the overall performance of MEMS resonator-based sensors, making the search
for new excitation methods a crucial area of research.
Recently, a novel excitation scheme called Blue Sideband Excitation(BSE) has been
proposed, which can simultaneously excite multiple modes of the MEMS resonator and
significantly enhance output amplitude and sensor sensitivity. This new method opens
the door to substantial performance improvements for MEMS-based sensing applications, however, there has been little research on it so far.
The goal of this project is to develop a sensor interface based on the BSE technique
for MEMS resonators. The proposed interface incorporates a transimpedance amplifier
(TIA), a phase-locked amplifier, and an automatic amplitude control module. This paper presents a comprehensive theoretical analysis, detailed design specifications, and
performance testing of the interface.It is the first on chip sensor interface based on BSE.
The final implementation is set to undergo tape-out in April 2024.

In this thesis, a direction-reconfigurable wide-input-range radio frequency energy harvesting
system is described. In order to improve the receiving power and the performance in low
power range, three blocks of optimization are placed in different part of the system. Subse
quently, a two paths 3-stage body biased cross-coupled differential-drive rectifier with antenna
beam forming control and 3-bit capacitor bank is designed and fabricated in a standard 180nm
CMOS technology. The rectifier is brought at resonance with four high-Q patch antennas by
means of a control loop that compensates for any variation at the antenna-rectifier interface
and a beam forming control that change the largest receiving direction of the antennas to allow
higher power input in multiple directions. A body-bias method with cross-coupled capacitors
and a diode to limit the body-bias voltage makes the rectifier works better in low power range.
The chip is integrated with four patch antennas. Measurements in an anechoic chamber at
2.45 GHz demonstrate a–10dBm sensitivity for 1 V output across a capacitive load. The
end-to-end power conversion efficiency reaches 65% at–6dBm.

Switched-capacitor power converters (SCPCs) have emerged as promising alternatives to traditional inductive power converters due to their CMOS integration capability and configurable conversion ratios. However, challenges such as output ripple, power efficiency, and transient response have hindered their widespread adoption. This article presents a novel Hybrid Hysteresis-CFM (HHC) control strategy that effectively addresses these issues.

The HHC strategy combines the best of both worlds, integrating hysteresis control and Continuous Frequency Modulation (CFM) control. During transient moments, the system utilizes a coarse/fine frequency tuning approach to rapidly reach the target frequency. Simultaneously, hysteresis control ensures that overshoot and undershoot are kept within predefined limits, significantly reducing output ripple during load transitions.

To enhance performance and versatility, the proposed system employs a Recursive Switched Capacitor (RSC) topology with adaptive capacitor sizing and 10-phase time-interleaving. This configuration enables configurable voltage-conversion ratios (VCRs) and high power conversion efficiency (PCE) across a wide input-output range.

Experimental results validate the effectiveness of the HHC SCPC. It demonstrates minimal overshoot and undershoot during load transition, maintains a low output voltage ripple during steady-state operation, and achieves high PCE. Comparative analysis with state-of-the-art DC-DC converters underscores the superior performance of the proposed system.

In summary, the Hybrid Hysteresis-CFM (HHC) control strategy offers a promising solution to enhance the capabilities of switched-capacitor power converters. Its ability to address output ripple, power efficiency, and transient response challenges makes it a valuable innovation for diverse applications requiring efficient power conversion.

The growing demand for asynchronous data communication leads to a growing demand for CDR systems to recover the sampling clock of the received data. The DTC in the CDR system is the main jitter source of the recovered data. A low-jitter DTC is required to generate data of low-jitter performance, calling for the application of a phase noise filter. Currently, most phase noise filters are based on the charge injection technique, which can only filter the phase noise of the DLL-based DTC.

This thesis presents a new phase noise filter, which can filter both the DLL and PI phase noise. The proposed phase noise filter is inspired by the noise transfer function from the phase detector’s input to the delay locked loop(DLL) output of a type-II DLL, which shows a first-order low-pass transfer function. The noise suppression pole frequency is adjustable and can be modified by changing the
gain of each component in the circuit. In addition, by carefully placing the frequency of the LDO’s pole, second-order noise filtering can be realized.

During design, a 10-bit DTC is constructed first and the proposed filter is placed behind the DTC to verify the effectiveness of the filter. The design achieves the post-layout level. The simulation results show that the DTC’s phase noise drops from 1.099 psrms to 315.9 fsrms with the filter. The area is 695 μm × 693.5 μm. The design consumes 42.3 mW with 1.8V supply in 180nm BCD technology.

With the great application potential of the Internet of Things (IoT), a reliable power supply solution for IoT plays an important role during the development of IoT and other advanced applications. Among all the options including the electricity grid, batteries, and energy harvesting systems, the energy harvesting systems are considered with priority for the following advantages such as longevity and maintenance-free, environmental sustainability, integration with other electronics, continuous Operation, etc. Among all the energy harvesting systems with different energy sources from the ambient environment, thermoelectric energy harvesting systems have attracted much attention from researchers due to the qualities of ubiquitous temperature difference and stable power supply. Another reason for choosing thermoelectric energy is that with a bipolar temperature difference across the material, an input voltage of either positive or negative polarity is generated to be harvested during the day and night. This is to say, with a bipolar input thermoelectric energy harvesting system, the IoT devices can be powered for a super long period of 90\% of the whole day. However, the system has to solve the problem of low input voltage from the thermoelectric generator(TEG).

To design a real thermoelectric energy harvesting system, there are several indispensable blocks including the start-up block, maximum power point tracking(MPPT), zero current switching(ZCS), and polarity detection. The start-up block is necessary to be implemented to provide a higher voltage available to turn on the transistors and help the system get rid of the cold state. The MPPT block is exploited to track the maximum power point where the equivalent resistance of the DC-DC converter is equal to the internal resistance of the TEG. The ZCS block is implemented is make sure after the discharging of the inductor inside the DC-DC converter, the power switch is precisely turned off to minimize the synchronization loss. The polarity detection block makes sure that the system always works in a proper state to harvest either positive or negative input voltage.

This article presents a 2-switch bipolar boost converter with 40 mV Photovoltaic(PV)-assisted startup voltage for a thermoelectric energy harvesting system. The power stage is configured as a bipolar boost converter for the bipolar input with the implementation of complementary transistors. And a buck-boost converter is configured for the input polarity transition. The proposed system was fabricated in a 180-nm BCD process. The measurement results show that the system can start up from the cold state with a TEG voltage as low as 40 mV. It boosts input voltages ranging from 40 mV to 0.3 V and from -40 mV to -0.3 V to a 1.2 V output voltage across the load. It achieves a peak end-to-end efficiency of 93.0\% with a 0.26V input voltage or 89.0\% with a -0.27V input voltage. Moreover, end-to-end efficiencies are higher than 80\% for input voltages from 120 mV to 0.3 V and from -120 mV to -0.3 V.

The development of the Internet of Things has given rise to enormous new industries and applications, including automobiles, smart healthcare systems, smart houses, etc, and the power supply has become the major constraint preventing them from further increasing logic speed. Thus, a SC(switch-capacitance) DC-DC converter with high efficiency, integration on-chip, and multiple voltage conversion ratio (VCRs) is significantly important.SAR(successive Approximation Register) SC was published in 2013, it realized 2n − 1 voltage conversion ratios with n 2:1 SC stage with the cost of charge sharing loss. In 2014, Recursive topology minimized charge-sharing loss by maximizing the connection to the power rail to improve efficiency. While both topologies only offer 7 VCRs for 3 stages, the new topology utilizing the voltage negative feedback technique has expanded this range to 79 ratios, including all p/q rational ratios from 1/2 to 15/16.Each ratio is written in the form Vout=A ∗ VDD − B ∗ Vout, and only three voltage negative feedback module(negators) are to be used :VDD −Vout,2VDD −Vout,−Vout.This paper presents an improved design to expand this VCR range to boost operation, achieving VCR from 15/16 to 16 times the input.
In total,3 2:1 SC stages and 3 negators are applied, with a total capacitance of 1.3nF. The
capacitance of 3 stages and negators are 130p,260p,520p, and 130p respectively. The system
was designed and fabricated in a 180-nm BCD process, the peak efficiency is achieved at a 2:1
ratio @20MHz, with an efficiency of 82.28%, reached load current =6.4mA. The layout area is
approximately 2.084mm2 , and the current density estimated is 3.07 mW/mm2. The design has remarkably expanded the 79 VCR options to both buck operation and boost operation

Resonant switch-capacitor (ReSC) is a type of hybrid switched-capacitor (HSC) which utilizes both inductor and capacitor, bearing the potential to overpower conventional switched-capacitor (SC) and magnetic-based converters. This work introduces a novel four-phase series-parallel resonant switch-capacitor (ReSC) DC-DC converter topology, which provides 16-to-1 conversion ratio and can serve as the unregulated first stage of two-stage 48V step-down voltage regulated module (VRM) for data centers. This topology can be treated as the cascade of one 4-to-1 SC stage and one 4-1 series parallel stage, the latter stage could reduce current stress on corresponding capacitors. The proposed converter uses 16 GaN switches, 5 flying capacitors and 1 inductor under the soft-switching condition. Phase changes under zero current switching (ZCS) conditions which greatly reduce their degradation to switches and extend their lifespan. Subsequently, when this topology serves as the first stage of two-stage VRM it could generate a 3V intermediate voltage, reducing voltage stress on the second regulation stage compared with a conventional 12V intermediate bus. A discrete prototype validates the analysis and achieves a fixed 16:1 conversion ratio, 96.5\% peak efficiency, and up to 460W/in$^3$ power density with a 48-V input voltage level.

A triboelectric nanogenerator (TENG) is a new transducer utilizing contact electrification and electrostatic induction to transduce mechanical energy into electric energy. Due to its high energy density and flexibility, it can be employed to make electronic devices self-powered by ambient mechanical energy in many application scenarios, such as biomedical devices, wearable electronics, and Internet-of-Things (IoT) sensors. However, it is challenging to extract electrical energy from TENG due to its time-varying and low internal capacitance. IC technology is advantageous in triboelectric energy harvesting (TEH) and power management with low leakage current and active harvesting configurations. Currently, studies on dedicated integrated power conversion techniques are very limited. Due to the exponentially increasing research interests in TENG, a comprehensive study on the TENG energy harvesting system, emphasizing IC power conversion techniques, is urgently needed.

Therefore, this project contains two parts. The first part is summarizing and comparing the state-of-the-art in TEH, as well as the advanced techniques employed in other kinetic energy harvesting such as piezoelectric and electrostatic energy harvesting. The potential of mature IC energy extraction techniques in TEH is emphasized. This part of work is collected and summarized in a literature review, which is being reviewed by IEEE Transactions on Circuit and System: I. For the rest of this thesis, a dedicated TEH interface employing Synchronized-Switch harvesting on Capacitor (SSHC) and Maximum Power Point Tracking (MPPT) working at 70 V is proposed, with theoretical analysis, design details, and simulated performance elaborated in this thesis. This is the first fully-integrated active rectifier reported for TEH. It is going to be fabricated on April 2023.

Depth sensing technology has developed rapidly recently due to its broad applications. Time-of-Flight (ToF) is a popular technology in depth sensing because of its advantages in high measuring accuracy and low complexity in image processing. ToF technologies are divided into two kinds: indirect time-of-flight (iToF) and direct Time-of-Flight (dToF). Compared to the iToF, dToF can detect targets at a longer distance by directly calculating the flight time of the laser. To obtain time information, the dToF system requires a Time-to-Digital Converter (TDC). This thesis proposes a system-level model to optimize the TDC parameters for a dToF system used in an autofocus system of a mobile phone. According to the simulation result of the system modeling, a ring-based TDC is chosen and built using a shared and duty-cycled Voltage-Controlled Oscillator (VCO). To decrease the DNL of the TDC, chopping comparators are used in this design. In addition, to save power and area, a new method called double sampling is used to align the coarse and fine phases of the ring based TDC. The proposed TDC achieves a resolution of 100 ps and a DNL of −0.27/+0.37 and an average power of 0.179 mW/TDC, which are smaller than that of state-of-the-art TDCs used in dToF systems. SMIC 55BSC technology is used to design and tape out the TDC.

This article presents a novel wide operational range reconfigurable regulating rectifier for wireless power transfer. The proposed 1X/2X/3X rectifier achieves wide range voltage regulation without global loop control to minimize the area occupation. Compared with previous work, more working modes and greater magnification allow the proposed rectifier to regulate smaller signal, which extends voltage regulation range. A novel local loop control system is proposed for voltage rectification with three modes. The local loop adaptively senses the duty cycle of mode signal to determine which two working modes the rectifier should work with and configure the rectifier in these two modes. Then the rectifier are switching between two working modes according to the comparison result with reference voltage. Also, the change of which two working modes are also triggered by a window comparator to make sure the change happens when the output voltage is far away from reference voltage. The system is designed and simulated in a 0.18um BCD technology. The measurement results show that the proposed system can rectify wide-range input AC power to a regulated output. The achieved voltage conversion ratio (VCR) is 0.95-2.68 with a peak power conversion efficiency (PCE) of 87.4%.