This paper presents a thermoelectric energy harvesting (TEH) interface that realizes: 1) a multi-channel TEH for maximum power point tracking (MPPT) under uneven temperature conditions, improving efficiency by up to 39.6%; and 2) a tapped-inductor start-up functionality, which can begin operating at 62mV with no additional inductors or series switches. The overall design achieves a 90.51% peak end-to-end efficiency. ... Read more

This paper presents an on-chip switched-capacitor converter, named piggybacked SC-on-CSCR, featuring: 1) a power density of 5.67mW/mm2 enabled by eliminating high-voltage switches and jointly utilizing MOM and MOS capacitors; 2) a 12-to-60V input and 1.8-to-5V output achieved through a chip-level modular design; 3) 71.5% peak efficiency enabled by full soft-charging operation; and 4) fast high-voltage startup protection, verified under a 20V/ms power-on slope. ... Read more

When driving a GaN switch, the maximum transition speed of drain-source voltage (peak dv/dt) should meet specification. But reducing the peak dv/dt usually exacerbates V-I overlap loss. This work presents a GaN driver for buck converter featuring: 1) voltage-controlled peak dv/dt; 2) almost constant dv/dt during Miller Plateau (MP) for reducing V-I overlap loss. We analyze why a constant dv/dt minimizes V-I overlap loss under a peak dv/dt specification, how to maintain a constant dv/dt during the MP period, and propose an implementable solution. We use a sensing block to judge whether the peak dv/dt violates the specification, and an adaptive searching scheme to find out the key parameters for the targeted constant dv/dt. We designed the layout with a 180-nm SOI process, and simulation results show that the peak dv/dt is well under control. It saves up to 33.99% V-I overlap loss when compared with the conventional constant current driver scheme. ... Read more

High-frequency buck converters need a fast transition of switching nodes (high dv/dt). Such high dv/dt, especially the positive one, can cause malfunction of a conventional pulse-triggered active-coupled (PTAC) level shifter that is used to control the high-side NMOS switch. In this work, we first discuss the dv/dt immunity of conventional PTAC level shifters. Subsequently, we propose a new scheme to block the noise current during the dv/dt sequence, allowing an almost full immunity to the positive dv/dt. With this scheme, the maximum dv/dt is determined by how well the circuitry is protected from the overvoltage during the dv/dt sequence. We design a 20-V buck converter with this level shifter, fabricated in 180-nm BCD process. Experimental results show it works correctly under a 67-V/ns dv/dt. ... Read more