This article presents a reconfigurable piezoelectric harvester array (RPA) designed for multi-input systems, which dynamically configures its structure based on the intensity of ambient vibrations. The proposed architecture enhances system efficiency by eliminating dc–dc converters and achieving maximum power point tracking through a single power stage. It also widens the input range by serially connecting PEH units, enabling operation at lower excitation levels. Additionally, this series connection reduces equivalent parasitic capacitance, improving flip efficiency and maximum output power improving rate (MOPIR).The proposed RPA is employed with classical parallel-synchronous switch harvesting on inductor technology and implemented using a 180 nm CMOS process. Experimental results demonstrate a conversion efficiency of up to 78%, an MOPIR of 5.93, and a minimum input voltage of 0.36 V. This highly integrated, wide-input-range, and energy-efficient scheme offers a novel approach to miniaturizing PEH systems. We present detailed design principles, operational mechanisms, and performance metrics, highlighting the RPA’s potential as a scalable and environmentally friendly solution for powering next-generation Internet of Thing devices.

Synchronized rectifiers offer promising solutions for piezoelectric energy harvesting; however, achieving the promised energy extraction performance necessitates using either a bulky inductor or multiple large capacitors, which cannot be on-chip integrated and increase the system form factor. This article introduces a fully integrated sequenced synchronized switch harvesting on capacitors (3SHC) rectifier. The input piezoelectric transducer (PT) uses microelectromechanical system technology. The cantilever is equally split into multiple strongly coupled subcantilevers, with each cantilever treated as an individual PT connected to the proposed rectifier. The 3SHC rectifier cyclically operates multiple times to synchronously flip the voltage of each cantilever sequentially. With the proposed design, all the flying capacitors only need to match the capacitance of each subcantilever; hence, they can be fully integrated on-chip. The design is fabricated using standard 0.18 μ m CMOS technology. Measurement results show that the proposed 3SHC rectifier attains an 80% voltage flip efficiency and achieves a 730% power enhancement compared to a full-bridge rectifier.

This article proposes a novel collaborative-flip synchronized switch harvesting on capacitors (CF-SSHCs) rectifier and multioutput synchronous dc-dc converters with shared capacitors. Compared to the traditional SSHC, our CF-SSHC rectifier can increase the number of flipping phases, potentially enhancing the flipping efficiency and output power under specific conditions where C FLY is close to C_P. The synchronous dc-dc converters reuse the flying capacitors to achieve a high maximum output power improving rate (MOPIR) over a limited input power range and provide multiple outputs. This work achieves an advanced number of flipping phases in capacitor-based rectifier interface technology and explores multiple-input multiple-output configurations, evaluating the system's performance under periodic and shock conditions for the first time. The system's adaptability to various piezoelectric transducer (PT) array configurations is validated, highlighting its potential for Internet of Things (IoT) networks. The design is fabricated in standard 0.18- μ m CMOS. Measurement results demonstrate that the voltage flipping efficiency of up to 83% is achieved. Compared with full-bridge rectifier (FBR), the MOPIR can be increased to 5.06 × and 4.78 × under off-resonance and on-resonance excitation, respectively. It can also achieve a 2.14 × power enhancement under shock excitation. Additionally, when the input power P INFBR is in the range of 1.42-28.4 μ W, the MOPIR of the proposed system is always greater than 4.

This article proposes a novel eight-phase self-bias-flip piezoelectric energy harvesting interface with charge recycling and reusing (SBFRR) and a switched-piezoelectric energy harvester (PEH) dc–dc (SPDC) converter. The proposed scheme innovatively utilizes the inherent capacitors ( CP ) of four PEHs as energy sources, flying capacitors, and flipping capacitors for time-sharing reuse to achieve both a high-voltage flipping and dc–dc conversion efficiency, while avoiding the use of extra energy reservoirs. The design is fully integrated and fabricated in standard 0.18- μ m CMOS. Measurement result demonstrates that the voltage flipping efficiency of up to 80% is achieved. Compared with the ideal full-bridge rectifier (FBR), the measured maximum output power improving rate (MOPIR) can be increased to 4.88 × . In addition, with the four CP serving as flying capacitors to achieve SPDC conversion for maximum power point track (MPPT), an MOPIR of > 3.5 × can be maintained with a PEH input voltage from 0.78 to 4.9 V.

This article presents a piezoelectric energy harvesting (PEH) interface circuit using a new self-bias-flip with the charge recycle (SBFR) technique without employing any additional energy reservoir. Traditional designs, including synchronous-switch harvesting on inductor (SSHI), synchronous-switch harvesting on capacitor (SSHC), synchronous electric charge extraction (SECE), etc., require additional capacitors or inductors to reverse the voltage on the PEH at the zero-crossing point. This design innovatively uses the inherent capacitors of the piezoelectric harvesters as the flipping capacitors. In order to improve the extract efficiency of the interface, the zero-crossing state is split into a charge recycle stage and a voltage-flip stage. For a piezoelectric array with 2^n PEHs, a configuration with (n-1) phases in the charge recycle stage is adopted to reduce the loss caused by direct charge neutralization. The charge redistribution loss is reduced by employing (2n+1) phases in the voltage-flip stage. The proposed principle has been implemented with discrete components and is verified by three different prototypes. The measurement results show that a flipping efficiency of 67% is achieved by utilizing SBFR with four PEHs. And the proposed interface can provide up to 5.2x improvement when compared with the full-bridge rectifier (FBR).

In this article, we propose a reconfigurable regulating rectifier with a wide operational range for wireless power transfer. The proposed three-mode rectifier achieves a broad range voltage regulation without global loop control to minimize the chip area occupation. Compared with previous work, more working modes and greater voltage gain allow the proposed rectifier to regulate lower input power, which extends the voltage regulation range. A local loop control scheme is proposed for voltage rectification with three modes. It adaptively senses the duty cycle of the mode signal to determine the working mode of the rectifier, and configure the rectifier to the desired mode for voltage regulation. The proposed system was designed and fabricated in a 180-nm BCD technology with an active area of 1.17 mm2. The measurement results show that the proposed system can rectify wide-range input ac power to a regulated output. The achieved voltage conversion ratiois between 0.95X and 2.68X, with a peak power conversion efficiencyat 87.4%.

Multiple voltage conversion ratio (VCR) recursive switched-capacitor (SC) dc-dc converters, based on several basic 2:1 converters, are widely used for on-chip power supplies due to their flexible VCRs for higher energy efficiency. However, conventional multiple VCR SC converters usually have one or more 2:1 converters unused for some VCRs, which results in lower power density and chip area wastage. This article presents a new recursive dc-dc converter system, which can dynamically reconfigure the connection of all on-chip 2:1 converter cells so that the unused converters in the conventional designs can be reused in this new architecture for increasing the load-driving capacity, power density, and power efficiency. To validate the design, a 4-bit-input 15-ratio system was designed and fabricated in a 180-nm BCD process, which can support a maximum load current of \text{0.71}\,\text{mA} and achieves a peak power efficiency of 93.1% with 105.3\,\mu \text{A/mm} {2} chip power density from a 2-V input power supply. The measurement results show that the load-driving capacity can become 6.826×, 2.236×, and 2.175× larger than the conventional topology when the VCR is 1/2, 1/4, and 3/4, respectively. In addition, the power efficiency under these specific VCRs can also be improved considerably.