This article presents a reconfigurable piezoelectric harvester array (RPA) designed for multi-input systems, which dynamically configures its structure based on the intensity of ambient vibrations. The proposed architecture enhances system efficiency by eliminating dc–dc converters and achieving maximum power point tracking through a single power stage. It also widens the input range by serially connecting PEH units, enabling operation at lower excitation levels. Additionally, this series connection reduces equivalent parasitic capacitance, improving flip efficiency and maximum output power improving rate (MOPIR).The proposed RPA is employed with classical parallel-synchronous switch harvesting on inductor technology and implemented using a 180 nm CMOS process. Experimental results demonstrate a conversion efficiency of up to 78%, an MOPIR of 5.93, and a minimum input voltage of 0.36 V. This highly integrated, wide-input-range, and energy-efficient scheme offers a novel approach to miniaturizing PEH systems. We present detailed design principles, operational mechanisms, and performance metrics, highlighting the RPA’s potential as a scalable and environmentally friendly solution for powering next-generation Internet of Thing devices.

This article proposes a novel collaborative-flip synchronized switch harvesting on capacitors (CF-SSHCs) rectifier and multioutput synchronous dc-dc converters with shared capacitors. Compared to the traditional SSHC, our CF-SSHC rectifier can increase the number of flipping phases, potentially enhancing the flipping efficiency and output power under specific conditions where C FLY is close to C_P. The synchronous dc-dc converters reuse the flying capacitors to achieve a high maximum output power improving rate (MOPIR) over a limited input power range and provide multiple outputs. This work achieves an advanced number of flipping phases in capacitor-based rectifier interface technology and explores multiple-input multiple-output configurations, evaluating the system's performance under periodic and shock conditions for the first time. The system's adaptability to various piezoelectric transducer (PT) array configurations is validated, highlighting its potential for Internet of Things (IoT) networks. The design is fabricated in standard 0.18- μ m CMOS. Measurement results demonstrate that the voltage flipping efficiency of up to 83% is achieved. Compared with full-bridge rectifier (FBR), the MOPIR can be increased to 5.06 × and 4.78 × under off-resonance and on-resonance excitation, respectively. It can also achieve a 2.14 × power enhancement under shock excitation. Additionally, when the input power P INFBR is in the range of 1.42-28.4 μ W, the MOPIR of the proposed system is always greater than 4.

With the advent of the lnternet-of-Things (1oT) era, sensor nodes are required in almost all fields to achieve a better interaction between humans and the environment. Piezoelectric energy harvester (PEH), which exhibits an equivalent electrical model of an AC current source /P in parallel with the inherent capacitor CP, is a promising technology to resolve the energy problem of such sensor nodes. Recently, inductor-based rectifiers, capacitor-based rectifiers and hybrid rectifiers have been proposed to improve the energy extraction efficiency of PEH devices [1]–[5]. However, these structures all require the aid of additional capacitors or inductors to achieve bias-flip operation, as illustrated in Fig. 1. These extra passive devices are typically large, which can be a major bottleneck in system-volumeconstrained applications such as MEMS [4]. In response to the above problem, this work proposes a novel 8-phase self bias-flip PEH interface with charge recycling and reusing (SBFRR). By using the C P of 4 PEHs as flipping capacitors, this scheme achieves a high voltage flipping efficiency without using extra energy reservoirs. The 4 C P can also serve as flying capacitors to achieve switched-PEH DC-DC (SPDC) conversion for MPPT, while maintaining a MOPIR of >3.5× with a PEH input voltage (Vp) from 0. 78Vto4.9V.

This article proposes a novel eight-phase self-bias-flip piezoelectric energy harvesting interface with charge recycling and reusing (SBFRR) and a switched-piezoelectric energy harvester (PEH) dc–dc (SPDC) converter. The proposed scheme innovatively utilizes the inherent capacitors ( CP ) of four PEHs as energy sources, flying capacitors, and flipping capacitors for time-sharing reuse to achieve both a high-voltage flipping and dc–dc conversion efficiency, while avoiding the use of extra energy reservoirs. The design is fully integrated and fabricated in standard 0.18- μ m CMOS. Measurement result demonstrates that the voltage flipping efficiency of up to 80% is achieved. Compared with the ideal full-bridge rectifier (FBR), the measured maximum output power improving rate (MOPIR) can be increased to 4.88 × . In addition, with the four CP serving as flying capacitors to achieve SPDC conversion for maximum power point track (MPPT), an MOPIR of > 3.5 × can be maintained with a PEH input voltage from 0.78 to 4.9 V.

This article presents a piezoelectric energy harvesting (PEH) interface circuit using a new self-bias-flip with the charge recycle (SBFR) technique without employing any additional energy reservoir. Traditional designs, including synchronous-switch harvesting on inductor (SSHI), synchronous-switch harvesting on capacitor (SSHC), synchronous electric charge extraction (SECE), etc., require additional capacitors or inductors to reverse the voltage on the PEH at the zero-crossing point. This design innovatively uses the inherent capacitors of the piezoelectric harvesters as the flipping capacitors. In order to improve the extract efficiency of the interface, the zero-crossing state is split into a charge recycle stage and a voltage-flip stage. For a piezoelectric array with 2^n PEHs, a configuration with (n-1) phases in the charge recycle stage is adopted to reduce the loss caused by direct charge neutralization. The charge redistribution loss is reduced by employing (2n+1) phases in the voltage-flip stage. The proposed principle has been implemented with discrete components and is verified by three different prototypes. The measurement results show that a flipping efficiency of 67% is achieved by utilizing SBFR with four PEHs. And the proposed interface can provide up to 5.2x improvement when compared with the full-bridge rectifier (FBR).